Patents Represented by Attorney, Agent or Law Firm David E. Steuber
  • Patent number: 6172383
    Abstract: A MOSFET contains a voltage clamp including one or more diodes which connects its gate and source. The voltage clamp is designed to break down at a predetermined voltage and thereby protect the gate oxide layer from damage as a result of an excessive source-to-gate voltage. The voltage clamp generally contains one or more parallel branches connected between the source and gate terminals of the MOSFET. Each branch contains at least one diode and in many cases a series of diodes that, depending on the clamping voltage desired, are connected so that they either break down or conduct in a forward direction when the gate-to-source voltage reaches a selected level. To achieve a lower clamping voltage the diode or diodes are typically connected so that they conduct in a forward direction, and to achieve a higher clamping voltage the diode or diodes are connected so that they undergo avalanche breakdown. In many instances a given branch contains diodes that are connected in different directions (e.g.
    Type: Grant
    Filed: May 5, 1999
    Date of Patent: January 9, 2001
    Assignee: Siliconix incorporated
    Inventor: Richard K. Williams
  • Patent number: 6171096
    Abstract: A generally flat rectangular pencil blank made from a composite celluosic and resin material or cross-linking agent includes a longitudinal axis, a first surface and a second surface with a repeatable profile transverse to the longitudinal axis on the first surface of the blank, the profile representing an approximate peripheral shape of a repeated series of longitudinal sections of an outside peripheral portion of a series of parallel elongated pencils, and an integral web between each adjacent pair of the series of longitudinal sections and extending to the second surface. In one embodiment, the second surface further includes a series of spaced parallel longitudinal grooves for reception of pencil cores, formed on the second surface and positioned laterally so as to be aligned to an apex of each repeatable profile. Methods of making the pencil blanks including dies and molds for making the pencil blanks are also disclosed.
    Type: Grant
    Filed: August 30, 1999
    Date of Patent: January 9, 2001
    Assignee: California Cedar Products Company
    Inventor: Laurence R. Hood
  • Patent number: 6167893
    Abstract: A dynamic chuck for holding a semiconductor wafer or other substrate includes a plurality of clamping arms mounted radially about a central axis of rotation of the wafer or other substrate. Each of the arms is mounted such that it is free to pivot about a horizontal axis. As the chuck rotates the substrate, a centrifugal force acts on each of the arms, causing it to pivot about its axis of rotation and thereby forcing a holding surface of the arm against a peripheral edge of the substrate. The dynamic chuck is applicable to any type of device in which a semiconductor wafer or other substrate must be held in a centered positioned while it is being spun, including wafer cleaning and rinsing apparatus.
    Type: Grant
    Filed: February 9, 1999
    Date of Patent: January 2, 2001
    Assignee: Novellus Systems, Inc.
    Inventors: Steven W. Taatjes, John F. Ostrowski
  • Patent number: 5471498
    Abstract: A data transceiver includes a transmitter connected at one end of a data transmission line and a receiver connected at the other end of the data transmission line. At least some portions of the transceiver are formed in CMOS. A temperature compensation circuit is connected to selected components of the transceiver to correct for temperature-induced variations in currents through those components. The temperature compensation circuit includes a pair of transistors connected, respectively, in parallel conduction paths. The respective width-to-length ratios of the channels of the transistors are unequal, and their gates are tied together. The current through the larger transistor varies directly with temperature, and this current is reflected in a current mirror transistor that is connected to the shorted gates of the transistor pair.
    Type: Grant
    Filed: April 15, 1993
    Date of Patent: November 28, 1995
    Assignee: National Semiconductor Corporation
    Inventor: James R. Kuo
  • Patent number: 5438300
    Abstract: A frequency multiplier includes a ring oscillator having a number of logic gates arranged in a plurality of rings. Control inputs enable the selection of individual gates so as to connect them into the ring or, conversely, remove them from the ring. As additional gates are removed, the combined delay imposed by the gates remaining in the ring is reduced and the frequency of the oscillator increases. A variable delay element, preferably a group of tri-state inverters connected in parallel, is connected between two of the gates. The oscillator is fine tuned by controlling the delay inserted by the variable delay element. The frequency multiplier also includes a frequency comparator. A reference frequency is passed through a divide-by-K unit and the output of the ring oscillator is passed through a divide-by-N unit, N being greater than K.
    Type: Grant
    Filed: April 1, 1994
    Date of Patent: August 1, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Rami Saban, Avner Efendovich, Varda Karpati
  • Patent number: 5426539
    Abstract: A multiple-gap head for transferring data to or from a storage medium is disclosed. Data read by the gaps are directed over a plurality of serial data paths where the data are processed and synchronized. In some embodiments, all or part of a data synchronizer is shared by the serial data paths. The data are then assembled into a parallel data stream for delivery to a computer. Reading the data simultaneously with multiple gaps increases by several times the rate at which data can be transferred to or from a storage medium. In accordance with another aspect of the invention, a three-gap head is provided to reduce or eliminate the cross-talk or noise fringe problems which reduce the track density in a storage medium. A signal attenuator and a signal inverter are connected to each of the side gaps and the outputs thereof are summed with the signal originating at the center gap, such that the inverted signals from the side gaps cancel any cross-talk originating at the center gap.
    Type: Grant
    Filed: December 1, 1992
    Date of Patent: June 20, 1995
    Assignee: National Semiconductor Corporation
    Inventors: William D. Llewellyn, Robert J. Strain
  • Patent number: 5416442
    Abstract: An improved Class A amplifier has an enhanced slew rate response at high frequencies. A positive feedback path is connected from the output of the amplifier to a point on the gain path. The feedback path includes a capacitor, a resistor and a transistor, the resistor being connected between the base and emitter of the transistor. At relatively high frequencies, the voltage drop across the resistor causes the transistor to turn on, forming a buffered positive feedback path through an additional resistor. The amount of feedback is controlled by the second resistor in the feedback path. In the preferred embodiment, dual feedback paths are connected between the output terminal and different points in the gain path.
    Type: Grant
    Filed: March 1, 1994
    Date of Patent: May 16, 1995
    Assignee: National Semiconductor Corporation
    Inventor: Stephen W. Hobrecht
  • Patent number: 5379242
    Abstract: A ROM filter includes a number of ROMs, each of which is programmed to hold data relating to several pulse response curves during only a particular time interval. As data are read into the filter, data pertaining to a particular pulse response curve are addressed in each of the ROMs. The outputs of the ROMs are connected to an adder, which adds the data read from the ROMs and passes it through a digital-to-analog converter. In this arrangement, the ROMs are required to store only the data relating to the pulse response curves during a particular interval. These data are added together in real time in an adder which is external to the ROM. With this structure the area of the ROM can be significantly reduced, as compared with ROM filters in which the addition is programmed into the ROM.
    Type: Grant
    Filed: September 1, 1993
    Date of Patent: January 3, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Dennis M. Rose, Daniel E. Fague
  • Patent number: 5093150
    Abstract: A method of synthesizing metal-containing material by a plasma chemical vapor deposition comprises converting a reactive gas containing metal atoms into plasmas in a reaction chamber and supplying an inert gas from outside the plasma region in the reaction chamber. Ceramic films of excellent quality can be synthesized under stable conditions in an industrial mass production process.
    Type: Grant
    Filed: March 14, 1990
    Date of Patent: March 3, 1992
    Assignee: Alps Electric Co., Ltd.
    Inventors: Yoshihiro Someno, Toshio Hirai, Makoto Sasaki
  • Patent number: 5032695
    Abstract: A membrane key switch includes a single resiliently deformable dielectric membrane with flaps cut therein which is formed in a housing such that the end of each flap covers a portion of the membrane. Conductive traces of the membrane are positioned so that downward flexing of the flap, caused by actuation of the switch, establishes electrical contact between a contact region on the flap end and a contact region on an uncut portion of the membrane.
    Type: Grant
    Filed: April 26, 1990
    Date of Patent: July 16, 1991
    Assignee: Alps Electric (USA), Inc.
    Inventor: Barry Mullins