Patents Represented by Attorney, Agent or Law Firm David E. Steuber
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Patent number: 6271060Abstract: This semiconductor surface mount package is relatively inexpensive to produce and has a footprint that is essentially the same size as the die. A conductive substrate is attached to the back side of a wafer and is in electrical contact with a terminal on the back side of each die in the wafer. A nonconductive overcoat is formed and patterned on the front side of the wafer, leaving a portion of the passivation layer and the connection pads for the dice exposed, each of the connection pads being coated with a solderable metal layer. The assembly is then sawed in perpendicular directions along the scribe lines between the dice, but the saw cuts do not extend all the way through the substrate, which remains intact at its back side. The parallel cuts in one direction are broken to produce die strips which are mounted, sandwich-like, in a stack, with one side of the strips exposed.Type: GrantFiled: September 13, 1999Date of Patent: August 7, 2001Assignee: Vishay Intertechnology, Inc.Inventors: Felix Zandman, Y. Mohammed Kasem, Yueh-Se Ho
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Patent number: 6268242Abstract: One or more diodes are connected in a conductive path between the source and gate of a vertical MOSFET to prevent the voltage between the gate and source from exceeding a predetermined level and thereby protect the gate oxide layer from damage. The diodes are formed in the same polysilicon layer that is used to form the gate of the MOSFET, by implanting N and P-type dopants into the layer. To minimize the number of additional processing steps required, at least one of these implants is performed simultaneously with the implanting of the source or body of the MOSFET. As an additional aspect of the invention, the metal contact to the source and body regions in a vertical planar DMOSFET is formed by fabricating a sidewall spacer on the gate of the MOSFET.Type: GrantFiled: May 19, 1999Date of Patent: July 31, 2001Inventors: Richard K. Williams, Wayne B. Grabowski
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Patent number: 6260241Abstract: A splicing nut for securing a line or rope enables quick, lightweight, secure attachment of the line or rope end to itself so as to form a loop. The loop can be used to attach to another line or an object without the use of a knot or other attachment means or device.Type: GrantFiled: September 14, 1999Date of Patent: July 17, 2001Inventor: Stephen Brennan
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Patent number: 6256200Abstract: A semiconductor package contains a plurality of sheet metal leads that are attached to one or more terminals on a top side of a semiconductor die. A heat sink is attached to a terminal on a bottom side of the die. Each of the leads extends across the die and beyond opposite edges of the die and is symmetrical about an axis of the die. At the locations where the leads pass over the edges of the die notches are formed on the sides of the leads which face the die, thereby assuring that there is no contact between the leads and the peripheral portion of the top surface of the die. Particularly in power MOSFETs the peripheral portion of the top surface normally contains an equipotential ring which is directly connected to the backside (drain) of the MOSFET, and hence a short between the leads on the top of the die and the equipotential ring would destroy the device. The result is a package that is extremely rugged and that is symmetrical about the axis of the die.Type: GrantFiled: May 27, 1999Date of Patent: July 3, 2001Inventors: Allen K. Lam, Richard K. Williams, Alex K. Choi
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Patent number: 6249277Abstract: A finger stylus for a touch screen includes a flexible non-metallic elastic ring or a flexible, fabric-like strap having distal ends, each of the distal ends includes parts of an interconnect fastener such as a hooks and loops or a magnetic fastener. The ring or strap forms a wraparound for a human fingertip such that, in use, the bonding of the interconnect fastener parts about the fingertip or the elasticity of the ring firmly hold the strap against the fingertip. The ring or strap includes an intermediate portion including a loophole extending from an exterior surface of the intermediate portion which receives a longitudinal stylus rod extending through the loophole in a semi-friction-fit connection with the loophole. The rod in use is positioned to extend through the loophole generally transversely to the strap and above and beyond a user's fingertip for touching a touch screen. The stylus rod is made of a non-marking material with generally rounded shaped ends.Type: GrantFiled: October 21, 1998Date of Patent: June 19, 2001Inventor: Nicholas G. Varveris
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Patent number: 6249041Abstract: An improved semiconductor device is disclosed. In one embodiment, the semiconductor device includes a semiconductor chip with contact areas on the top or bottom surface. A first lead assembly, formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to one of the contact areas of the semiconductor chip. The first lead assembly also has at least one lead connected to and extending from the lead assembly contact. A second lead assembly, also formed from a semi-rigid sheet of conductive material, has a lead assembly contact attached to another one of the contact areas of the semiconductor chip. The second lead assembly also has at least one lead connected to and extending from the lead assembly contact. An encapsulant encloses the semiconductor chip, the lead assembly contact of the first lead assembly and the lead assembly contact of the second lead assembly.Type: GrantFiled: June 2, 1998Date of Patent: June 19, 2001Assignee: Siliconix IncorporatedInventors: Y. Mohammed Kasem, Anthony C. Tsui, Lixiong Luo, Yueh-Se Ho
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Patent number: 6239463Abstract: A power MOSFET or other semiconductor device contains a layer of silicon combined with germanium to reduce the on-resistance of the device. The proportion of germanium in the layer is typically in the range of 1-40%. To achieve desired characteristics the concentration of germanium in the Si-Ge layer can be uniform, stepped or graded. In many embodiments it is desirable to keep the germanium below the surface of the semiconductor material to prevent germanium atoms from being incorporated into a gate oxide layer. This technique can be used in vertical DMOS and trench-gated MOSFETs, quasi-vertical MOSFETs and lateral MOSFETs, as well as insulated gate bipolar transistors, thyristors, Schottky diodes and conventional bipolar transistors.Type: GrantFiled: August 28, 1997Date of Patent: May 29, 2001Assignee: Siliconix incorporatedInventors: Richard K. Williams, Mohamed Darwish, Wayne Grabowski, Michael E. Cornell
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Patent number: 6219186Abstract: Low-cost plastic optics allow biocular viewing of video images with a single electro-optic display device. Folded and unfolded dual off-axis configurations use collimated illumination and intermediate imaging optics to fill both eyepieces from a single display device without requiring beamsplitters. Multiple illumination schemes provide either monochrome or color, either two-dimensional or time-sequential true stereographic presentation. Light from multicolor sources is superimposed using dichroic mirrors. A display field lens proximate to the display surface collimates the illumination beam. A shaping lens provides substantially uniform illumination of the display surface. An aperture stop improves image quality by blending sub-pixel higher order spatial harmonics from the display device. Offsetting color over- and under-correction of individual optical elements provides overall chromatic correction with minimal optical complexity.Type: GrantFiled: August 13, 1999Date of Patent: April 17, 2001Assignee: Optimize IncorporatedInventor: Raymond T. Hebert
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Patent number: 6214526Abstract: An antireflective layer for use in semiconductor photolithography is fabricated of silicon nitride (Si1−x−yNxHy) in a plasma-enhanced chemical vapor deposition process using a gaseous mixture of ammonia, silane and nitrogen. By varying the process temperature and the ratio of ammonia to silane, acceptable values of the refractive index n and extinction coefficient k can be obtained. The silicon nitride layer produced by this technique etches rapidly and therefore allows the antireflective layer to be removed quickly, thereby minimizing the damage to the underlying structures in a semiconductor device.Type: GrantFiled: February 17, 1998Date of Patent: April 10, 2001Assignee: Novellus Systems, Inc.Inventors: Srinivasan Sundararajan, Kenneth P. MacWilliams, David Mordo
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Patent number: 6214193Abstract: A plating cell has an inner plating bath container for performing electroplating on a work piece (e.g., a wafer) submerged in a solution contained by the inner plating bath container. A reclaim inlet funnels any solution overflowing the inner plating bath container back into a reservoir container to be circulated back into the inner plating bath container. A waste channel is also provided having an inlet at a different height than the inlet of the reclaim channel. After electroplating, the wafer is lifted to a position and spun. While spinning, the wafer is thoroughly rinse with, for example, ultra pure water. The spin rate and height of the wafer determine whether the water and solution are reclaimed through the reclaim channel or disposed through the waste channel.Type: GrantFiled: August 13, 1999Date of Patent: April 10, 2001Assignee: Novellus Systems, Inc.Inventors: Jonathan D. Reid, Steven W. Taatjes, Robert J. Contolini, Evan E. Patton
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Patent number: 6204677Abstract: A testing apparatus has a load board and a device under test electrically interconnected with the load board. A pressure jig, which has a forcing unit and a structural member for fixing a fixed portion of the forcing unit with respect to the load board, also has a pressure actuating component moveable with respect to the fixed portion of the forcing unit. The pressure actuating component contacts the device under test. The apparatus may include a probe that contacts a terminal of the device under test for monitoring the signal state of the terminal as the device under test interacts with the load board.Type: GrantFiled: September 22, 1998Date of Patent: March 20, 2001Assignee: Mosel Vitelic, Inc.Inventor: Bruce D. Hallgren
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Patent number: 6204533Abstract: A vertical trench-gated power MOSFET includes MOSFET cells in the shape of longitudinal stripes. The body diffusion of each cell contains a relatively heavily-doped region which extends parallel to the length of the cell and contacts an overlying metal source/body contact layer at specific locations. In one embodiment, the contact is made at an end of the cell. In another embodiment, the contact is made at intervals along the length of the cell. In addition, the power MOSFET contains diode cells placed at intervals in the array of cells. The diode cells contain diodes connected in parallel with the MOSFET cells and protect the gate oxide layer lining the trenches from damage due to large electric fields and hot carrier injection. By restricting the areas where the body contact is made and using the diode cells, the width of the MOSFET cells can be reduced substantially, thereby reducing the on-resistance of the power MOSFET.Type: GrantFiled: June 2, 1998Date of Patent: March 20, 2001Assignee: Siliconix IncorporatedInventors: Richard K. Williams, Wayne B. Grabowski
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Patent number: 6199506Abstract: A plasma-enhanced chemical vapor deposition system includes a balancing inductor in the circuit path between the radio frequency generator and the “showerhead” that is used to introduce reactant gases to the system. The balancing inductor reduces the resonant frequency of the circuit to a level below the frequency of the signal produced by the radio frequency generator. Since the effective capacitance of the showerhead electrode varies monotonically with the power input to the plasma, fluctuations in the power delivered to the plasma will be self-correcting the system will be stabilized. For example, a drop in the power to the plasma will reduce the resonant frequency, but the corresponding reduction in the effective capacitance of the showerhead electrode will tend to increase the resonant frequency, thereby offsetting the change and stabilizing the system.Type: GrantFiled: June 30, 1999Date of Patent: March 13, 2001Assignee: Novellus Systems, Inc.Inventors: Stephen Hilliker, Viral Hazari, Sriram Seshagiri, Zia Karim
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Patent number: 6193854Abstract: A hollow cathode magnetron (HCM) sputter source includes a main magnet positioned near the sidewall of the hollow cathode target and a pair of rotating magnet arrays that are positioned near the closed end of the hollow cathode target. One of the arrays produces a magnetic field that is aligned with (aids) the magnetic field produced by the main magnet; the other arrays produce a magnetic field that is aligned against (bucks) the magnetic field produced by the main magnet. Field lines produced by the magnet arrays contain an extension of the plasma that is controlled by the main magnet. Charged particles circulate between the two portions of the plasma. The extended plasma is thus formed over a very high percentage of the surface of the target, thereby creating an erosion profile that is highly uniform and encompasses essentially the entire face of the target. This maximizes the utilization of the target and minimizes the frequency at which the spent target must be replaced.Type: GrantFiled: August 16, 1999Date of Patent: February 27, 2001Assignee: Novellus Systems, Inc.Inventors: Kwok Fai Lai, Larry Dowd Hartsough, Andrew L. Nordquist, Kaihan Abidi Ashtiani, Karl B. Levy, Maximilian A. Biberger
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Patent number: 6193859Abstract: An apparatus for depositing an electrically conductive layer on the surface of a wafer comprises a flange. The flange has a cylindrical wall and an annulus attached to a first end of the cylindrical wall. The annulus shields the edge region of the wafer surface during electroplating reducing the thickness of the deposited electrically conductive layer on the edge region. Further, the cylindrical wall of the flange can be provided with a plurality of apertures adjacent the wafer allowing gas bubbles entrapped on the wafer surface to readily escape.Type: GrantFiled: May 7, 1998Date of Patent: February 27, 2001Assignees: Novellus Systems, Inc., International Business Machines CorporationInventors: Robert J. Contolini, Jonathan Reid, Evan Patton, Jingbin Feng, Steve Taatjes, John Owen Dukovic
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Patent number: 6185991Abstract: A microscope uses electrostatic force modulation microscopy to measure mechanical and electrical characteristics of a sample. A tip contacts the sample while a voltage (which may have dc and ac components) is applied between the tip and sample. The tip oscillates even though the tip is contacting the sample due to strong electrostatic force interaction between the tip and sample. Different characteristics of the sample such as hardness, surface potential, capacitance, surface charge, and so forth, are measured by manipulating the oscillation of the tip relative to the sample and monitoring the position of the tip.Type: GrantFiled: February 17, 1998Date of Patent: February 13, 2001Assignee: PSIA CorporationInventors: Jaewan Hong, Sang-il Park, Zheong-Gu Khim
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Patent number: 6179983Abstract: An apparatus for depositing an electrical conductive layer on the surface of a wafer includes a virtual anode located between the actual anode and the wafer. The virtual anode modifies the electric current flux and plating solution flow between the actual anode and the wafer to thereby modify the thickness profile of the deposited electrically conductive layer on the wafer. The virtual anode can have openings through which the electrical current flux passes. By selectively varying the radius, length, or both, of the openings, any desired thickness profile of the deposited electrically conductive layer on the wafer can be readily obtained.Type: GrantFiled: November 13, 1997Date of Patent: January 30, 2001Assignee: Novellus Systems, Inc.Inventors: Jonathan David Reid, Steve Taatjes
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Patent number: 6180185Abstract: An apparatus for forming a film on a substrate includes a gas inlet and an insert attached to the gas inlet, the insert including a deposition source material such as lithium. To form the film on the substrate, the substrate is mounted in a vacuum chamber. After the vacuum chamber is pumped down to a subatmospheric pressure, a first process gas such as argon is provided through the gas inlet and insert and into a plasma region proximate the substrate. Power is then coupled to generate a plasma inside of the insert which heats the insert and causes the deposition source material to vaporize. The deposition source material vapor is mixed with a plasma polymerizable material in the plasma region proximate the substrate causing a plasma enhanced chemical vapor deposition (PECVD) thin film such as silicon oxide including the deposition source material (e.g. lithium) to be deposited on the substrate.Type: GrantFiled: November 30, 1999Date of Patent: January 30, 2001Inventor: John T. Felts
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Patent number: 6179973Abstract: A novel hollow cathode magnetron source is disclosed. The source comprises a hollow cathode with a non-planar target. By using a magnet between the cathode and a substrate, plasma can be controlled to achieve high ionization levels, good step coverage, and good process uniformity.Type: GrantFiled: June 30, 1999Date of Patent: January 30, 2001Assignee: Novellus Systems, Inc.Inventors: Kwok F. Lai, Andrew L. Nordquist, Kaihan A. Ashtiani, Larry D. Hartsough, Karl B. Levy
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Patent number: 6177142Abstract: An apparatus for forming a film on a substrate includes a gas inlet and an insert attached to the gas inlet, the insert including a deposition source material such as lithium. To form the film on the substrate, the substrate is mounted in a vacuum chamber. After the vacuum chamber is pumped down to a subatmospheric pressure, a first process gas such as argon is provided through the gas inlet and insert and into a plasma region proximate the substrate. Power is then coupled to generate a plasma inside of the insert which heats the insert and causes the deposition source material to vaporize. The deposition source material vapor is mixed with a plasma polymerizable material in the plasma region proximate the substrate causing a plasma enhanced chemical vapor deposition (PECVD) thin film such as silicon oxide including the deposition source material (e.g. lithium) to be deposited on the substrate.Type: GrantFiled: June 2, 1999Date of Patent: January 23, 2001Inventor: John T. Felts