Patents Represented by Attorney, Agent or Law Firm David L. Smith
  • Patent number: 6725018
    Abstract: In accordance with the present invention, a communications system transmits a predetermined signal, from a first, sending, end of a communications system to a second, receiving, end of a communications system. The predetermined signal is distorted by the communication system and is received as a distorted signal that is compared to a known version of the originally transmitted signal. A comparison signal related to the difference between the originally transmitted signal (as represented by the known version of the originally transmitted signal) and the distorted predetermined signal as received at the receiving end is employed to adjust the transfer characteristic of a programmable converter to compensate for the distortion introduced by the communication system.
    Type: Grant
    Filed: September 18, 2000
    Date of Patent: April 20, 2004
    Assignee: Agere Systems Inc.
    Inventor: George Francis Gross, Jr.
  • Patent number: 6683465
    Abstract: A stress migration test structure is provided that can be used to detect stress migration defects in traces or conductors of integrated circuits. The stress migration test structure can be placed between die areas on a wafer, or on a die. On the die, a stress migration test structure can be placed in otherwise unused areas of a die such as between bond pads and the periphery of a die, in a layer beneath bond pads, in a region between the bond pads and the perimeter of standard area for circuit layout, or in regions in more than one level of the integrated circuit. The stress migration test structure may also be placed within the standard area for circuit layout and used, with some additional circuitry, as a stress migration test structure on an integrated circuit once the die is packaged. Obtaining information from the impedance segments of a stress migration test structure can be accomplished employing either a mechanical stepping or an electrical stepping technique.
    Type: Grant
    Filed: October 31, 2001
    Date of Patent: January 27, 2004
    Assignee: Agere Systems Inc.
    Inventors: H. Scott Fetterman, Vivian Ryan
  • Patent number: 6640324
    Abstract: An integrated circuit includes a semiconductor die having a plurality of input/output pads and a plurality of boundary scan cells. Each of the boundary scan cells includes a TDI input and a TDO output. A first boundary scan cell is the first boundary scan cell of the plurality of boundary scan cells to receive data. A last boundary scan cell is the last boundary scan cell of the plurality of boundary scan cells to receive data. An endless control conductor forms a loop proximate the plurality of boundary scan cells. The endless control conductor is coupled to each of the plurality of boundary scan cells to provide a test clock signal thereto. At least one other control conductor extends around the semiconductor die proximate the plurality of boundary scan cells. The at least one other control conductor is discontinuous between the first and last boundary scan cells.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: October 28, 2003
    Assignee: Agere Systems Inc.
    Inventor: Alexander Goldovsky
  • Patent number: 6507317
    Abstract: An electronic device having a retractable antenna is disclosed. The antenna is spring loaded and extends beyond the profile of the housing of the electronic device when in use. The antenna is retracted to within the profile of the housing of the electronic device when not in use. Preferably the antenna is spring loaded to move from the retracted position to the extended position upon actuation. Preferably, the antenna is a quadrifilar antenna. The antenna may be incorporated in an on-off switch.
    Type: Grant
    Filed: August 11, 2000
    Date of Patent: January 14, 2003
    Assignee: Agere Systems Inc.
    Inventor: Alexander E Kalish
  • Patent number: 6449629
    Abstract: An integrated circuit includes an adder having a first adder circuit for receiving a portion of the operands to be summed, along with corresponding carry-in inputs. The first adder circuit provides a sum output and carry-out outputs. A second adder circuit receives another portion of the operands to be summed, along with corresponding carry-in inputs. Multiplexers between the first and second adder circuits determine whether the carry-in inputs to the second adder circuit are the same the carry-in inputs to the first adder circuit or whether the carry-in inputs to the second adder circuit are independent.
    Type: Grant
    Filed: May 12, 1999
    Date of Patent: September 10, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventor: Edward Clayton Morgan
  • Patent number: 6407645
    Abstract: There is disclosed a first stub short bonded across conductive runners of a tuning stub at a distance preferably greater than a distance resulting in the desired frequency of operation of a voltage controlled oscillator tuned by the tuning stub. Thereafter, the voltage controlled oscillator is powered and tested to determine the frequency of operation of the voltage controlled oscillator. The position of a second stub short is determined based on the frequency of oscillation of the oscillator due to the presence of the first stub short, the geometry of the tuning stub and the desired frequency of operation of the voltage controlled oscillator. A second stub short is precisely positioned along the stub using automated equipment, relative to the position of the first stub short, to result in the desired frequency of operation of the voltage controlled oscillator.
    Type: Grant
    Filed: January 31, 2000
    Date of Patent: June 18, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: William Edward Fulmer, Michael J Koziel, Curtis J Miller, Mark J Nelson, Johannes Gerardus Ransijn
  • Patent number: 6404364
    Abstract: A multistage converter and method for converting a sampled analog signal to a corresponding digital representation. Each stage of the converter receives an analog input signal and produces a partial digital output. A first stage receives the sampled analog signal as the analog input signal. Each stage provides a residue output, which is the analog input signal to a subsequent stage. The residue is the analog input signal to the stage, less the analog equivalent of the partial digital output from the stage, possibly with a gain change. A voltage range over which a sample of an analog signal can vary is defined by a lower limit and an upper limit. A lower comparator threshold is established within the voltage range. An upper comparator threshold is established within the voltage range, between the lower comparator threshold and the upper limit. The analog input to the stage is quantized based on the lower and upper comparator thresholds to generate a quantized sampled analog signal.
    Type: Grant
    Filed: August 24, 2000
    Date of Patent: June 11, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: H. Scott Fetterman, David Arthur Rich
  • Patent number: 6400208
    Abstract: An integrated circuit includes a pulse generator for generating a pulse of a predetermined duration. A first switch, controlled by the pulse, drives current into a fuse link when the pulse takes on a first logic level. The first switch prevents flow of current into the fuse link when the pulse takes on a second logic level. A latch is coupled to the fuse link to sense a logic level developed during the pulse. The latch may be cleared by the leading edge of the pulse. The logic level developed at the fuse link due to the driven current is latched into the latch by the trailing edge of the pulse and is indicative of whether the fuse link was blown or not blown.
    Type: Grant
    Filed: August 9, 2000
    Date of Patent: June 4, 2002
    Assignee: Agere Systems Guardian Corp.
    Inventors: Mark K Lesher, Douglas D Lopata
  • Patent number: 6329877
    Abstract: There is disclosed a power amplifier includes an in-phase power splitter generating two split signals from an input signal, and two amplifiers capable of operating in different modes. The split signals are provided as respective inputs to the two amplifiers which are coupled through transmission lines such that as the first amplifier approaches the maximum power it can produce, the output from the second amplifier begins to contribute to the power amplifier output and supplements and modifies the power provided by the first amplifier thereby extending the range of input power over which the power amplifier delivers output power.
    Type: Grant
    Filed: June 25, 1999
    Date of Patent: December 11, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: John Wayne Bowen, Roger Anthony Fratti, James Daniel Yoder
  • Patent number: 6278393
    Abstract: There is disclosed an integrated circuit including a digital-to-analog converter in which a resistor string is adapted to be coupled to a reference source. The resistor string includes a plurality of serially coupled impedances defining intermediate taps at the junctions thereof. A first plurality of switches are coupled between a first output node and respective ones of the intermediate taps. A first selection circuit receives a first digitally coded signal and is coupled to each switch in the first plurality of switches. The first selection circuit selectively switches the first plurality of switches to predetermined states depending upon a first digitally coded signal provided thereto, to generate a first analog output. A second plurality of switches are coupled between a second output node and respective ones of the intermediate taps.
    Type: Grant
    Filed: August 12, 1999
    Date of Patent: August 21, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Douglas D. Lopata, Malcolm Harold Smith
  • Patent number: 6272188
    Abstract: The invention includes a method of identifying an extremum value and an index in a group of values where each value has an associated index. A count register is initialized to an initial count. A value from the group as well as a predetermined value are provided simultaneously to an arithmetic logic unit and a multiplexer. The value from the group and the predetermined value are compared in the arithmetic logic unit. A selector is set to one of a first or second logic state. In the first logic state the selector selects a minimum; in the second logic state the selector selects a maximum. One of the value and the predetermined value are selected as an extremum based on a flag set by the comparison in the arithmetic logic unit and the selector. The predetermined value is replaced with the extremum and the count register count is stored when the selector is set to a first state and the value is less than the predetermined value.
    Type: Grant
    Filed: May 8, 1998
    Date of Patent: August 7, 2001
    Assignee: Agere Systems Guardian Corp.
    Inventors: Mohammad Shafiul Mobin, Sivanand Simanapalli, Larry R. Tate
  • Patent number: 6173161
    Abstract: In accordance with the present invention, a communications system transmits a predetermined signal, from a first, sending, end of a communications system to a second, receiving, end of a communications system. The predetermined signal is distorted by the communication system and is received as a distorted signal that is compared to a known version of the originally transmitted signal. A comparison signal related to the difference between the originally transmitted signal (as represented by the known version of the originally transmitted signal) and the distorted predetermined signal as received at the receiving end is employed to adjust the transfer characteristic of a programmable converter to compensate for the distortion introduced by the communication system.
    Type: Grant
    Filed: September 15, 1997
    Date of Patent: January 9, 2001
    Assignee: Lucent Technologies Inc.
    Inventor: George Francis Gross, Jr.
  • Patent number: 6172629
    Abstract: There is disclosed, a converter for converting an input signal from one form to another. The converter includes a slicing circuit adapted to slice a signal into levels. The slicing circuit includes at least one threshold for establishing slicing levels. Dither is employed to vary at least one slicing level in the slicing circuit.
    Type: Grant
    Filed: February 19, 1998
    Date of Patent: January 9, 2001
    Assignee: Lucent Technologies Inc.
    Inventor: H. Scott Fetterman
  • Patent number: 6163563
    Abstract: A receiver for a spread spectrum communication system is disclosed in which a transmitter transmits a data signal to a receiver includes a memory for storing digital representation of the data signal received by the receiver. A memory input addressing unit defines a circulating data window. A first ring shift register circulates a first set of components of a spreading code. A second ring shift register circulates a second set of components of a spreading code. A selector selects one of the first set of components or the second set of components as selected components of the spreading code and an adder receives as inputs digital representations of the data signal from the circulating data window and the selected components of the spreading code. The adder provides an output that is the dot product of the inputs.
    Type: Grant
    Filed: December 23, 1997
    Date of Patent: December 19, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Thomas Wesley Baker, Richard Adam Cesari, Ravi Kumar Kolagotla
  • Patent number: 6157338
    Abstract: An integrated circuit which includes a successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter employs oppositely coupled comparators and logic circuitry to generate a signal upon a bit determination, with the signal latching the determined bit, resetting the comparators for the subsequent bit determination, and if additional bit(s) are to be determined, commencing the subsequent bit determination. The converter may be configured as a single ended, differential or complimentary circuit.
    Type: Grant
    Filed: February 23, 1999
    Date of Patent: December 5, 2000
    Assignee: Lucent Technologies Inc.
    Inventor: George Francis Gross, Jr.
  • Patent number: 6154165
    Abstract: An integrated circuit includes a variable bit-depth successive approximation analog-to-digital converter. The variable bit-depth successive approximation analog-to-digital converter can select from at least two clock signals of different frequencies to drive the variable bit-depth successive approximation converter for each bit depth application. Within each bit-depth application, the converter may employ more than one clock frequency.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: November 28, 2000
    Assignee: Lucent Technologies Inc.
    Inventor: George Francis Gross, Jr.
  • Patent number: 6154164
    Abstract: There is disclosed an integrated circuit including a successive approximation analog-to-digital converter. The successive approximation analog-to-digital converter can select which of at least two clock signals of different frequency drive the successive approximation converter for each bit determination. Each bit determination may employ a different clock frequency, or a particular clock frequency could be used for multiple bit determinations. The clock signals may be generated within the analog-to-digital converter, or the clock signal may be provided to the analog-to-digital converter.
    Type: Grant
    Filed: September 16, 1998
    Date of Patent: November 28, 2000
    Assignee: Lucent Technologies Inc.
    Inventor: George Francis Gross, Jr.
  • Patent number: 6150885
    Abstract: There is disclosed a transconductance amplifier receives a voltage input and provides a current output. The transconductance amplifier includes a current mirror having a lowpass filter between transistors implementing the current mirror.
    Type: Grant
    Filed: June 24, 1999
    Date of Patent: November 21, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Kirk Burton Ashby, Brian K. Horton
  • Patent number: 6122655
    Abstract: A multiplier generates an array of partial products. The partial products are reduced in a converter having cells defining rows and columns. Cells adjacent to adders alternate between a cell that provides non-inverted outputs and a cell that provides inverted outputs, such that alternate rows of cells operate on non-inverted data and the intervening rows of cells operate on inverted data. A multiplexer for receiving the outputs from a row of cells may be an inverting multiplexer or a non-inverting multiplexer depending on the cell arrangement.
    Type: Grant
    Filed: May 15, 1998
    Date of Patent: September 19, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Alexander Goldovsky, Ravi Kumar Kolagotla
  • Patent number: RE36894
    Abstract: Disclosed is a semiconductor package which permits coupling of semiconductor bond pads to I/O leads where a high density of connections is needed. Conductive fingers backed by an insulating tape are bonded to the ends of the ringers on a lead frame. The tape fingers are electrically coupled to the bond pads on one major surface of the semiconductor chip by wire bonding. In one embodiment, the opposite major surface of the chip is bonded to a paddle on the lead frame through an aperture in the tape for maximum heat dissipation.
    Type: Grant
    Filed: April 19, 1994
    Date of Patent: October 3, 2000
    Assignee: Lucent Technologies Inc.
    Inventors: Lawrence Arnold Greenberg, David Jacob Lando