Abstract: A multifunctional chip includes first and second electrically isolated bonding pads. The chip also includes a control circuit coupled to the second bonding pad. The control circuit commands the chip to perform the first function if the first and second bonding pads are coupled. Alternatively, the control circuit commands the chip to perform the second function if the first and second bonding pads remain electrically isolated. The coupling or isolation between the first and second bonding pads is determined by wire bonds. Therefore, the use of wire bonds selects the function for the chip.

Abstract: There is disclosed an integrated circuit including a phase detection circuit having an exclusive gate having first and second gate inputs for receiving first and second gate input signals. The exclusive gate provides at an output, a gate output signal that is the exclusive combination of the first and second gate input signals. A first switched resistance is coupled between a first voltage source and a common node. A second switched resistance, coupled between a second voltage source and the common node, receives the gate output signal of the exclusive gate to control the effective resistance thereof. The first and second resistances develop a signal at the common node. A comparator has a first input coupled to the common node and a second input coupled to a threshold value.

Abstract: A technique for efficiently utilizing memory in determining a next state accumulated cost in a communications system or a Viterbi decoder. The system includes a memory having an array of registers. A first present state accumulated cost is retrieved from a first storage register of the array. A second present state accumulated cost is retrieved from a second storage register of the array. A first next state accumulated cost is calculated based on the first present state accumulated cost. The first next state accumulated cost is stored in the first storage register of the array. An advantage of the invention is that such a technique requires less memory to calculate and store accumulated costs. The number of memory locations required is one for each individual state, which is substantially half of the memory locations required previously.

Abstract: There is disclosed an integrated circuit that includes a digital-to-analog converter having a resistor string driven by a current source. The resistor string is coupled to the current source. Intermediate taps are defined at the resistor junctions as well the resistor-current source junctions. Switching transistors are coupled between an output node and a respective intermediate tap. A selection circuit is coupled to a terminal of each switching transistor for selectively switching the transistors to a predetermined state to electrically couple the associated intermediate tap to the output node.

Abstract: A voltage-to-current converter comprises a first MOS transistor for receiving a voltage signal at a first gate and transferring a current signal between a first drain and a first source, a second MOS transistor for receiving a biasing voltage at a second gate and transferring the current signal between a second drain and a second source, and a biasing circuit for applying the biasing voltage of V.sub.C +V.sub.T +kV.sub.DS to the second gate such that the second transistor provides a substantially constant drain-to-source resistance of 1/.beta.V.sub.C, where V.sub.C is a constant voltage, V.sub.T is a threshold voltage for the second transistor, V.sub.DS is a drain-to-source voltage for the second transistor, k is a constant in the range of 1/3 to 2/3, and .beta. is a gain for the second transistor.

Abstract: Disclosed is an integrated circuit comprising a balanced set of inputs and a phase splitting circuit. The phase splitting circuit has a first input terminal that is coupled to the balanced set of inputs and a second input terminal that is coupled to the balanced set of inputs. The phase splitting circuit further comprises a balanced phase shifting network, a first set of output terminals, and a second set of output terminals. The balanced phase shifting network is coupled to the first: input terminal and the second input terminal. The first set of output terminals provides a voltage representative of a first voltage across a resistive portion of the balanced phase shifting network in response to an input voltage at the balanced set of inputs. The second set of output terminals provides a voltage representative of a second voltage across a reactive portion of the balanced phase shifting network in response to the input voltage at the balanced set of inputs.

Abstract: There is disclosed a digital-to-analog converter including a resistor string having intermediate taps at resistor junctions as well as resistor-potential junctions. Switching transistors are coupled between a respective intermediate tap and an output node. Decode circuits are capable of switching at least two transistors to be in the on state at the same time to electrically couple more than one intermediate tap to the output node to produce at least one analog output. In one embodiment, one row select line can be energized simultaneously with at least two column select lines. Alternatively, at least two row select lines can be energized simultaneously with one column select line. A DAC in accordance with the present invention is suitable for fabrication in the form of a monolithic integrated circuit and requires less area while maintaining the same degree of resolution as prior art DACs. The DAC also may be used with successive approximation circuitry to provide an analog-to-digital converter.

Abstract: A reduced speed equalizer is provided which receives signal samples at a first rate but performs the equalizing operation at a second, lower rate which is below the rate at which symbols are transmitted across the channel. The equalizer is docked to receive samples in a shift register at the first rate. Samples stored in the shift register are clocked into a set of buffers at the second rate. The equalizer coefficients are applied to the samples stored in the buffer set to generate a sequence of equalized symbols at the second rate.

Abstract: In accordance with an embodiment of the invention, a data converter is disclosed employing at least one minimum phase FIR filter. The data converter includes an analog-to-digital converter for converting an incoming analog signal into a plurality of digital signal samples, followed by a minimum phase FIR filter to filter the digital signal samples. Alternatively, the data converter includes a digital-to-analog converter preceded by a minimum phase FIR filter to filter a plurality of digital signal samples that are converted into an analog signal by the digital-to-analog converter. The data converter may include both analog-to-digital and digital-to-analog conversion. In a preferred embodiment, the minimum phase FIR filter is an optimum minimum phase FIR filter. A method for precisely calculating the filter coefficients of an optimum minimum phase FIR filter is also disclosed.

Abstract: In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.

Abstract: An integrated circuit is disclosed that includes a sense amplifier having first and second transistors, each of which have a conduction path and a gate electrode. The conduction path of the first and second transistors are electrically coupled in series between a power supply node and an input. The integrated circuit also includes third and fourth transistors each having a conduction path and a gate electrode. The conduction path of the third and fourth transistors are electrically coupled in series between the power supply node and a first reference potential. The gate electrodes of the first and third transistors are electrically coupled to an output node. A fifth transistor has a conduction path electrically coupled between a second reference potential and the output node. The gate electrode is maintained at a voltage that is about two threshold voltage drops below the voltage level of the power supply node.

Abstract: There is disclosed an integrated circuit including a sense amplifier. The sense amplifier is capable of encoding 2.sup.n levels of output characteristic into a bit pattern of n corresponding bits. The sense amplifier includes a non-zero detect circuit for detecting when the output characteristic is zero. The sense amplifier also includes 2.sup.n -2 comparators for comparing an output characteristic to 2.sup.n -2 reference levels when the output characteristic is non-zero. The 2.sup.n -2 reference levels are constructed from 2.sup.n -2 non-zero levels of the 2.sup.n possible levels of output characteristic. An encoder is coupled to the non-zero detect circuit and the comparators. The encoder encodes the output from the non-zero detect circuit and the outputs from the comparators to corresponding predetermined bit patterns. When the output characteristic is determined to be zero by the non-zero detect circuit, the bit pattern output is a default bit pattern.

Abstract: A digital communication system including Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. The trellis of surviving branch data is stored in an array of registers. Operating the system includes initiating a first traceback from a storage register at a first symbol instant. The traceback traces a path back through the trellis a first predetermined number of symbol instants to determine a first decoded symbol. A second traceback is also initiated at the first symbol instant and traces a path back through the trellis a second predetermined number symbol instants to determine a second decoded symbol. The first traceback length may be greater than or less than the second traceback length. In another embodiment of the invention several tracebacks can be executed having a fixed traceback length, followed by other tracebacks having incrementally different traceback lengths.

Abstract: There is disclosed an integrated circuit including a resistive material runner resistor string comprising a series of resistors in which each resistor includes at least one runner direction change feature. Each resistor includes first and second contiguous elements. The junction of the first and second elements form a direction change feature such as a corner in the runner of the resistor string. Taps are positioned along the resistor string at substantially equal resistance intervals. The first and second elements may be squares of different edge dimensions. The resistor string is useful in applications such as digital-to-analog converters.

Abstract: The integrated circuit includes a plurality of row decoder-driver circuits, each for raising the voltage of a respective row line. Each of the plurality of row decoder-driver circuits includes an address decoder capable of receiving a plurality of address bits. The plurality of address bits, when decoded, identify one of the plurality of row decoder-drivers to provide an output. Each of the plurality of row decoder-drivers has an input transistor having a gate. The input transistor has a conduction path coupled between a power supply node and the address decoder. A signal generating circuit receives a signal to raise the voltage of a respective row line associated with the identified row decoder-driver circuit. The signal generating circuit provides an output that is coupled to the gate of the input transistor of each of the plurality of row decoder-driver circuits.

Abstract: A communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A matrix of surviving branch data is stored in an array of registers. Operating the system includes initiating a first traceback from a storage register at a first symbol instant. The traceback traces a path back through the trellis a first predetermined number of symbol instants to determine a first decoded symbol. The length of the traceback is changed and another traceback is executed. This process is repeated until all remaining final decoded symbols are decoded. In an alternate embodiment, the traceback length is repreatedly decremented by one less than the constraint length, with each traceback obtaining multiple decoded symbols.

Abstract: Convolutionally encoded information subjected to channel intersymbol interference is decoded by calculating the minimum cost path through a trellis. The trellis terminates in known states. Exploiting the open architecture of the coprocessor, the minimum cost state is checked to ascertain if it is the known, that is, correct state and if it is not, the possible known states are searched by the DSP inside the ECCP active register and the state with the lowest cost amont the possible states is selected.

Abstract: In accordance with an embodiment of the invention, a data converter is disclosed employing at least one minimum phase FIR filter. The data converter includes an analog-to-digital converter for converting an incoming analog signal into a plurality of digital signal samples, followed by a minimum phase FIR filter to filter the digital signal samples. Alternatively, the data converter includes a digital-to-analog converter preceded by a minimum phase FIR filter to filter a plurality of digital signal samples that are converted into an analog signal by the digital-to-analog converter. The data converter may include both analog-to-digital and digital-to-analog conversion. In a preferred embodiment, the minimum phase FIR filter is an optimum minimum phase FIR filter. A method for precisely calculating the filter coefficients of an optimum minimum phase FIR filter is also disclosed.

Abstract: A communication card includes a housing and a shank rotatably mounted thereto. The shank defines an axis along its length around which the shank can rotate. A connector is mounted on the shank. The shank and connector are extendable beyond an edge of the housing to an extended position. In the extended position, the connector and shank are rotatable about the shank axis.

Abstract: A digital communication system including a Viterbi decoder for tracing a path through a trellis of individual state information and method of operation are disclosed. The traceback determines a decoded symbol. A trellis of branch origin data is stored in an array of registers. The branch origin data associated with a symbol instant is a cell. Each cell of data is generated by execution of an update instruction form a digital signal process (DSP) to the coprocessor. A first predetermined traceback length is written to a traceback length register. The first predetermined traceback length is small to minimize tracebacks cycling into branch origin data from a previous transmission burst. A traceback is initiated by the DSP providing the coprocessor a single traceback instruction. The Viterbi decoder alternates between update and traceback instructions. At a predetermined symbol instant, the traceback length is increased to a second predetermined length by over-writing the traceback length register.