Abstract: A data converter is disclosed that includes a multiplier for multiplying digital signal samples by a gain factor to produce multiplied digital samples. The multiplier can either be bypassed or a dither signal can be introduced in the multiplication operation. A multiplexer responsive to a select input selectively provides either the digital signal samples or the multiplied digital signal samples as the output of the multiplexer.

Abstract: There is disclosed a soft symbol for use in a decoding process generated from a binary representation of a branch metric. When a hard decision bit is a zero, a preselected number of bits of a binary representation of the branch metric are concatenated with a hard decision bit to form the soft symbol. When the hard decision bit is a one, the ones complement of the preselected number of bits of the binary representation of the branch metric are concatenated with the hard decision bit to form the soft symbol. The concatenation function can be achieved using an exclusive OR function with the preselected bits of the binary representation of the branch metric and the hard decision bit to form the soft symbol. The hard decision bit may be selectable from more than one source.

Abstract: In accordance with the present invention, a technique for efficiently utilizing memory in determining which next state accumulated cost to retain, such as in a communication system or a Viterbi decoder. The system includes a memory having a portion of registers allocated to a first array and a portion of registers allocated to a second array. The technique includes retrieving a present state accumulated cost from a storage register of the first array and calculating a next state accumulated cost based on the present state accumulated cost. The next state accumulated cost is stored in a storage register of the second array. The second array is designated as containing present state accumulated costs. A present state accumulated cost is retrieved from a storage register of the second array and used in calculating a subsequent next state accumulated cost. The subsequent next state accumulated cost is stored in a storage register of the first array.

Abstract: In accordance with an embodiment of the invention, a data converter is disclosed that provides a sampling rate conversion. The converter receives a clock signal, a divided-down clock signal, and first digital signal samples at a first rate. The converter converts the first digital signal samples to second digital signal samples at a second rate. The ratio of the first rate to the second rate is defined as a fist conversion rate factor. A first programmable counter receives the clock signal and divides down the clock signal to produce a divided-down clock signal. The first programmable counter is programmable to selectively determine the first conversion rate factor.In an alternate embodiment, another stage of sampling rate conversion is provided by a second data converter. The second converter receives the divided-down clock signal, a further divided-down clock signal, and the second digital signal samples. The second data converter converts the second digital signal samples to the third rate.

Abstract: There is disclosed an integrated circuit having a buffer that includes an output driver for receiving data and for transferring the data to an output node to be placed on a bus. The buffer also includes a pull-up control device coupled to the output node. The control device is capable of being switched between a first state that couples the output node to a predetermined logic level and a second state that does not couple the output node to the predetermined logic level. Control logic coupled to the pull-up control device receives first and second logic signals to control the state of the control device. With the second logic signal in a first predetermined level, the first logic signal is capable of switching the control device to the first state when in a first predetermined state and to the second state when in a second predetermined state. The second logic signal when in a second predetermined level overrides the control of the first logic signal to maintain the control device in the second state.

Abstract: An integrated circuit includes a clock alignment circuit having a frequency synthesizer for receiving a reference clock signal at a lower frequency and for generating phases of an oscillator clock signal at a higher frequency. The oscillator clock signal phases drive a desired clock signal generating circuit that generates various phases of the desired clock signal. The desired clock signal phases are systematically compared to the reference clock signal. The phase of the desired clock signal that is determined to align with the reference clock signal is provided as the desired clock signal output from the integrated circuit such that there is no apparent time delay through the integrated circuit. In an alternate embodiment, a single phase of the desired clock signal is selected and a phase locked loop adjusts the oscillator in the frequency synthesizer to align the selected phase of the desired clock signal with the reference clock signal.

Abstract: There is disclosed of the invention, a data converter for converting a signal from one form to another converts signals from analog-to-digital or from digital-to-analog form. The converter has an analog side and a digital sample side. A programmable barrel shift selector on the digital side receives digital signal samples of a first bit field width and selects a second bit field width as the output. The second bit field width is programmable over a range to selectively determine which bits in the first bit field are included in the second bit field.

Abstract: A shielded member includes a nonconductive housing for mounting on a substrate. The housing includes a cavity and has a base to be received against the substrate. The housing includes at least one integral mounting post extending beyond the base for reception in respective aperture in the substrate. A conductive coating extends over at least a portion of the housing and at least a portion of the integral mounting post. The conductive coating provides shielding for the cavity with currents induced in the conductive coating on the housing conductible to a trace on the substrate by way of the conductive coating on the integral mounting post.

Abstract: In accordance with the present invention, a field programmable gate array includes at least one programmable function unit. The programmable function unit has first and second logic circuits, each providing an output, and first and second output drivers, each having an input. The input of each output driver is adapted to be selectively coupled to the output of either of the logic circuits. A programmable interconnection is provided to selectively couple the input of the two output drivers to the output of a selective one of the logic circuits.

Abstract: A transconductor includes first and second differential pair compound transistors coupled between a first reference node and a common node. The compound transistors are commoned to each other at a common node. A single current source is coupled between the common node and a second reference node. In an alternate embodiment, a current turnaround circuit may be used to convert the transconductor to a single ended configuration.

Abstract: A multiplexer for selecting one of at least two input signals as the output on sensing the change in the state of a select input waits for the clock signal of the active first clock to transition to a predetermined state, disconnects the active first clock from the output of the multiplexer and maintains the output of the multiplexer in the predetermined state while waiting for the clock signal of a second clock to transition to the predetermined state. The second clock is connected as the multiplexer output while the clock signal of the second clock is in the predetermined state. In a preferred embodiment, the predetermined state is a low logic level.

Abstract: An integrated circuit is disclosed that includes a biquadratic filter in which the poles and zeroes are independently adjustable. The transfer function of the filter has a pair of zeroes in the numerator and a pair of complex conjugate poles in the denominator. The integrated circuit includes a first circuit for constructing the complex conjugate poles of the filter transfer function. The first circuit has an input port for receiving an input signal and an output port at which an output current representative of a filtered output signal is presented. The integrated circuit includes a second circuit for constructing, independently of the poles, the zeroes of the filter transfer function. The second circuit has an input port coupled to the input port of the first circuit for receiving the input signal. The second circuit includes a differentiator for differentiating the input signal to produce a differentiated input signal.

Abstract: A stacked connector assembly is disclosed which includes two connectors attached to a bracket which, in turn, is attached to the surface of a printed circuit board. The bracket is of unitary construction and includes two side members interconnected by two lateral members. Openings are provided in the bracket through which solder tails of the two connectors extend. Each of the side members includes surface portions that mount to the connectors and to the printed circuit board.

Abstract: An integrated circuit for detecting harmonic lock of a phase-locked loop includes a frequency synthesizer for receiving a reference clock signal and for generating an oscillator clock signal. A phase generator receives the oscillator clock signal and generates a phase of the oscillator clock signal. A shift register receives as an input the reference clock signal and is clocked by the phase of the oscillator clock signal to produce an output that is a repetitive sequence of logic states. In an alternate embodiment, a harmonic decode circuit decodes the shift register output to determine which harmonic the phase-locked loop has locked onto.

Abstract: An electrical connector includes a connector body and an array of posts extending out at least one side of the connector body. Each of the posts defines a tip and two opposed pairs of post faces that intersect at edges extending along the post. The tip defines four tip faces which converge toward a tip nose, and each tip face is aligned with a respective one of the post faces. Each of the tip faces is convex outwardly, and the edges between the post faces adjacent the tip are curved with a radius of curvature greater than about 0.005 inches. The electrical connector is assembled by press fitting the posts through pre-formed through holes, and the tip geometry reduces skiving of material out of the through hole as well as assembly forces.

Abstract: A keyed electrical connector (2) includes a diecast housing (4) having a front face (20). A keying structure (26) which is an integral part of the housing (4) upstands from the front face (20). The keying structure forms a cylindrical protrusion (28) extending to a distal end (30). The cylindrical protrusions (28) defines an exterior surface having a radially outwardly extending rib (32). The rib (32) extends along at least a portion of the exterior surface of the protrusion (28).

Abstract: An integrated circuit for generating an oscillator clock signal based on a reference clock signal includes a wide band digital frequency detector. The wide band digital frequency detector includes a first shift register clocked by the reference clock signal and a second shift register clocked by the oscillator clock signal. A third shift register receives as an input the output from the first shift register and is clocked by the output of the second shift register. The third shift register provides a first oscillator control output. A fourth shift register receives a phase of the reference clock signal as an input and is clocked by the oscillator clock signal to provide a second oscillator control output. In an alternate embodiment, the first oscillator control output is coupled as the up-down control input of an up-down counter and the second oscillator control output is coupled as the clock input to the up-down counter to control the oscillator clock frequency.

Abstract: An integrated circuit has a signal path including a first circuit that introduces a propagation delay that decreases with circuit conditions and process speed in series with a second circuit that introduces a propagation delay that increases with circuit conditions and process speed. The circuit conditions and process speed are sensed and the duration of the propagation delay of the second circuit varied such that the total propagation delay remains within a predetermined range over circuit condition and process speed variations. In another embodiment of the invention, a current source develops a bias current to control the duration of the propagation delay of the second circuit. In yet another embodiment of the invention the current source is a current mirror.

Abstract: In the manufacture of integrated circuits, a process for forming a dielectric layer such as silicon dioxide which has a high wet etch rate is disclosed. Illustratively, the process is performed with a precursor gas in a plasma reactor with a shower head and a susceptor which supports a wafer. The power density, pressure, susceptor-shower head spacing, and (optionally) temperature are respectively decreased, decreased, increased and decreased to reduce the effectiveness of dissociation of the precursor gas. The resulting film contains impurities which enhance its wet etch rate.

Abstract: A ejector (12) for a memory card connector (10) having a host pin connector (18) adapted to receive a corresponding electrical connection terminal of a memory card (42) comprises a cover (54) disposed to receive a input force for controlled movement along memory card tracks (30) affixed to the host pin connector (18), the cover (54) having a cam engaging element (74). A cam lever (84) is pivotally mounted to said connector housing (14) includes a cam engaging surface (72) to receive the cam engaging element (84) and an ejector engaging element (106) disposed to linearly and rotationally engage the rear surface (126) of the memory card (42); whereby movement of the cover (54) actuates the cam lever (54) to cause said ejector engaging element (106) of the cam lever (68) to linearly and rotationally engage the electric terminal surface of the memory card (42) in a manner to disengage the memory card (42) from the host pin connector(s) (18).