Abstract: The voltage reference circuit is provided particularly but not exclusively for use in flash EPROM chips. The reference circuit is intended to be inhibited until proper start-up conditions have been established to allow the reference circuit to operate properly. This is achieved by incorporating an enable signal generating circuit which is responsive to start-up circuitry for generating an enable signal at an appropriate signal level.

Abstract: A heat sink for mounting a semiconductor chip in a plastic casing. The upper surface of the heat sink is in thermal contact with the semiconductor chip, the lower surface is coplanar with a main surface of the casing. The heat sink is formed from a substantially square sheet of metal having each of its corners folded as a tongue to provide a substantially square base, each of the folded tongues forming the lower surface of the base.

Abstract: A method whereby the N elements of a memory are read sequentially, and the data items contained therein are compared with reference data items. Simultaneously with the reading of each element of the memory, its address is written in a number of redundancy check registers, each connected to a respective redundancy element. In the event the element of the memory differs from the reference data item, the first of the redundancy check registers is blocked to prevent it from being overwritten and the address of a faulty element of the memory is permanently stored. Upon the entire memory being read, the addresses of any faulty elements in the memory are thus already stored in the redundancy check registers.

Abstract: A Zener diode is used to simplify a circuit for detecting the level of an operating voltage with respect to a specified range of use. The semiconductor junction of this Zener diode is biased alternately by one voltage or another. Under these conditions, the avalanche voltage of this Zener diode changes. The operating voltage to be monitored is connected to the cathode of this Zener diode. If the monitored operating voltage is higher than the avalanche voltage of this Zener diode, the diode alternately conducts. If the operating voltage is outside this range, this diode is either permanently on or permanently off. The variations that result therefrom are detected to report whether the operating voltage is correct.

Abstract: A digital delay line supplies from a periodic input signal n signals with the same period mutually shifted by one n-th of the input signal period. The digital delay line includes n cells, each of which includes m delay elements in series, each output of a delay element being connected to an input of a multiplexer. The output phase of the n-th cell is compared with that of the input signal phase. The output of a multiplexer of the n cells is modified after each comparison.

Abstract: A monolithic component incorporates a protection diode in parallel with a plurality of pairs of diodes having the same polarity. The monolithic component is formed from an N-type semiconductor substrate and includes P-type first regions that are formed at the upper surface of the substrate; second regions constituted by upper portions of the substrate, whose lateral surfaces are delineated by P-type insulating walls; a P-type third region at the bottom of the second regions; a fourth P.sup.+ -type region formed from the lower surface in the third region; a fifth N+-type region on the lower surface of the substrate; first metallizations connecting each of the first regions to each of the second regions; and a second metallization on at least one portion of the insulating wall.

Abstract: A semiconductor component is formed in a semiconductor wafer, of a first conductivity type. The semiconductor component includes a plurality of first regions, of a second conductivity type, in a top surface of the wafer and coated with a first metallization layer. The semiconductor component further includes a second region, of the second conductivity type, and a third region, of the first conductivity type, each formed in the top surface of the wafer. A second metallization layer coats the second and third regions. A fourth region, of the first conductivity type, is formed in a bottom surface of the semiconductor wafer and opposes the first and second regions. A fifth region, of the second conductivity type, is also formed in the bottom surface and opposes the third region. A rear surface metallization covers the bottom surface of the semiconductor wafer.

Abstract: A method and device for measuring the switching noise of an audio amplifier by measuring the energy of the noise signal at the output of the audio amplifier as the amplifier is switched from one operating condition to another by a control signal, and after first weighing the energy according to the frequency and volume sensitivity of the human ear. The device comprises a control signal generator; an audio band filter connected to the output of the audio amplifier; a meter for measuring the power of the filtered signal; and an integrating element for calculating the energy of the filtered signal.

Abstract: A circuit for squaring a binary number X of n bits, x.sub.0 to x.sub.n-1, includes pre-processing circuits to form a group of all the products x.sub.i y.sub.j of the bits of number X, where i and j vary between 0 and n-1 such that i.ltoreq.j. The outputs of the pre-processing circuits provide words such that each word is formed by a succession, as complete as possible, of products selected among the products remaining from the group of products after forming the preceding word, each product x.sub.i y.sub.j of this succession being affected with a weight i+j+1 of the word if i is different from j, or with a weight 2i if i=j. Adders are connected to sum the words as the square of the number X.

Abstract: A logic circuit has at least one first differential stage made of bipolar transistors operating in linear mode. The first differential stage is connected in a branch of a second differential stage biased by a current source. The second stage and the current source are made of MOS transistors.

Abstract: A multiple output current mirror comprising at least three mirror-connected PNP transistors whose bases are connected to a first node, at least three cascode-connected transistors, each cascode transistor being associated to one mirror transistor, a current input corresponding to the collector of the first cascode transistor, and mirror outputs corresponding to the collectors of the two other cascode transistors. The current mirror further comprising means for detecting the base current of each mirror transistor and for reproducing this base current on the collector of the cascode transistor to which each mirror transistor is associated.

Abstract: An integrated circuit memory device has: a memory array; a set of data latches for holding data bits to be stored in the memory array; a plurality of data tracks for supplying data bits to the data latches; a set of address latches for holding address bits for addressing the memory array; a test bus; a data bit routing circuit connected to the data latches for selectively routing data bits to either the memory array or the test bus; an address bit routing circuit connected to the address latches for selectively routing address bits to either the array or the test bus; and an output circuit for outputting data bits and address bits on the test bus. In this way, data bits and address bits can be checked for accuracy against the originally supplied data bits and address bits. Thus, a test can be conducted without requiring data actually to be written to memory cells of the memory.

Abstract: A monolithic protection semiconductor component is connected between a first semiconductor region apparent on a first surface of a semiconductor chip and a second semiconductor region apparent on a second surface. The first region is divided into several non-overlapping areas. Each area is connected to a common electrode through a fuse such as a gold filament.

Abstract: Integrated structure bipolar transistors with controlled storage time are manufactured by forming at least one bipolar transistor occupying a first area on a first surface of the silicon material, covering the first surface of the silicon material with an insulating material layer, and selectively removing the insulating material layer to open a window. The window has a second area much smaller than the first area occupied by the bipolar transistor. Therefore, by implanting into the silicon material a medium dose of platinum ions through the window and diffusing into the silicon material the implanted platinum ions, a uniform distribution of platinum inside the transistor is obtained.

Abstract: A control device for a low-pressure fluorescent lamp placed in an oscillating circuit comprises a circuit for the detection of the frequency of the current in the lamp to deliver an information element at output as a function of the lit or unlit state of the lamp. This information element may be used to activate a first circuit to detect the end of an alternation in the lamp or a second circuit to detect the end of an alternation in the lamp, making it possible to let the lamp work at the resonance frequency of the oscillating circuit or at a frequency higher than the resonance frequency.

Abstract: Process for producing metrological structures particularly for direct measurement of errors introduced by alignment systems, whose peculiarity consists in performing, on a same substrate, metrological alignment markings and processed alignment markings according to arrays of preset numerical size.

Abstract: A drive circuit fault detection device comprising a discriminating circuit generating a digital signal, the level of which indicates a fault; and an identifying circuit generating a binary-coded signal indicating the type of fault, i.e. ground shorting of the drive circuit or an open load. The discriminating circuit comprises a resistive network connected to the output of the drive circuit, for generating a voltage indicating correct connection of the load or a fault on the drive circuit and a comparator for comparing the generated voltage with a reference voltage and supplying the digital signal at its output. The identifying circuit comprises a current mirror circuit generating an output voltage having two different logic levels in the event of short circuiting or an open load, respectively, and a combination circuit for generating the binary-coded output signal.

Abstract: A filter acting on digital image signals for apparatus of the video type includes at least first and second processing units adapted to elect an image edge, each processing unit includes an inferential circuit operating on fuzzy logic, which has first and second input terminals and an output terminal, and first and second comparison elements each having first and second input terminals and an output terminal, the input terminals being intended for receiving discrete digital signals of an image. The output terminals of the first and second comparison elements in the first processing unit are respectively connected to the first and second input terminals of the inferential circuit included in the first processing unit, and the output terminals of the first and second comparison elements in the second processing unit are respectively connected to the first and second input terminals of the inferential circuit included in the second processing unit.

Abstract: A method for loading the memory of an electronic controller operating using fuzzy logic, whereby predetermined membership functions of logic variables, defined within a universe of discourse sampled in a finite number of points, are subjected to inference operations basically configured as IF/THEN rules with at least one front preposition and at least one rear implication. The controller includes a central control unit provided with a memory section for storing predetermined values of the membership functions which appear in the front or IF part of the fuzzy rules and have a predetermined degree of truth or membership. This method provides for storing the memory section the only values of those membership functions that have a value of the degree of membership other than zero at the points of the universe of discourse.

Abstract: A method of lowering the power absorbed by an interface circuit, in the "power-down" state thereof, as incorporated to a telephone exchange and connected to a telephone subscriber line, being of a type which comprises a monitoring circuit portion connected between the line and the exchange. The method involves the steps of,detecting the polarization level of a conductor in the line,comparing that level with a reference value by means of a comparator having an input connected to the line and an output connected to the input of the monitoring circuit portion,switching the interface circuit to a standby state on a higher level than the reference value being sensed,once again detecting the polarization level of the line, this time through the interface circuit, andactivating the telephone exchange when, on completion of the second detection step, the polarization level stays above the reference value.