Patents Represented by Attorney David M. Driscoll

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  • Self-configurable, dual bridge, power amplifier
    Patent number: 5621352
    Abstract: A self-configurable, dual bridge, power amplifier has a window comparator sensing the level of input signals fed to the amplifier which-drives a plurality of configuring switches capable of configuring the amplifier as a single bridge amplifier driving a first and a second loads connected in series or as two distinct bridge amplifiers each driving one of the two loads. As long as the two levels of the input signals remain comprised between a range defined by a negative voltage reference and a positive voltage reference, the amplifier is configured as a single bridge driving the two loads in series, thus reducing sensibly power dissipation. Several embodiments of the configuring means are shown.
    Type: Grant
    Filed: August 21, 1995
    Date of Patent: April 15, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Edoardo Botti, Guido Brasca
  • Detector of the presence of a transmission in a modem
    Patent number: 5621765
    Abstract: A detector of the presence of a transmission in a modem, including a circuit for determining the absolute value of a receive signal, a first averaging block of the absolute value and two first comparators with respect to two predetermined detection and loss thresholds of a transmission, and further including a second averager which is associated with two second comparators with respect to predetermined extreme thresholds which englobe the two detection and loss thresholds, the first averager having a high time constant with respect to the time constant of the second averager.
    Type: Grant
    Filed: September 11, 1995
    Date of Patent: April 15, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: William Glass
  • Digital phase-locked loop filter
    Patent number: 5619543
    Abstract: A digital phase-locked loop filter in which the incoming error signals are subject to at least one multiplication by a filtering coefficient before being digitally processed at each clock pulse to provide a filtered signal. The PLL filter includes a circuit which decrements the value of the filtering coefficients at each clock pulse during an initial operation period of the filter.
    Type: Grant
    Filed: August 30, 1994
    Date of Patent: April 8, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: William Glass
  • Bit line sensing in a memory array
    Patent number: 5619449
    Abstract: A memory comprises first and second arrays of memory cells organised in rows and column. The cells in each row are connected to respective wordlines and the cells in each column are connected to a respective bit line. Wordlines of the first array are addressable independently of the wordlines of the second array. A sense amplifier is provided to sense the differential between a signal on the bit line of a selected cell in one array and a reference signal. A current souce is selectively connectable to supply the reference signal for comparison with the signal on the bit line of the addressed array. The present invention allows capacitive balancing to be achieved without the need for dummy cells.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: April 8, 1997
    Assignee: SGS-Thomson Microelectronics Limited
    Inventor: David H. McIntyre
  • Integrated circuit device and test method therefor
    Patent number: 5619463
    Abstract: An integrated circuit device includes an oscillator; a counter; a switch for selectively connecting the oscillator to the counter in a test mode; and an output circuit for providing the output count generated by the counter for determining the frequency of the oscillator. Thus, use is made of the normal on-chip counter in an integrated circuit to provide a reliable way of measuring the frequency of the on-chip oscillator.
    Type: Grant
    Filed: August 24, 1995
    Date of Patent: April 8, 1997
    Assignee: SGS-Thomson Microelectronics Limited
    Inventor: Vijay Malhi
  • Method for the erasure of a memory, and circuits for the implementation thereof
    Patent number: 5619451
    Abstract: A method for erasing a non-volatile electrically erasable and programmable integrated circuit memory that is divided into N sectors selected separately by addressing circuits and the cells for each sector being selected by row and column addressing circuits wherein an erasure pulse is applied simultaneously to all the sectors. The checking of the erasure of each sector leads to the locking of the sector when no defect is detected. A new erasure pulse is applied only to the unlocked sectors and only the unlocked sectors are rechecked. Also, a circuit for locking sectors in order to implement the method is disclosed.
    Type: Grant
    Filed: April 12, 1995
    Date of Patent: April 8, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Claude Costabello, Jean-Marie Gaultier
  • Fuzzy logic based scanning rate converter
    Patent number: 5619271
    Abstract: A television signal scanning conversion device of the type comprising at least one filtering block having a plurality of digital inputs which receive through an interface components of an interlaced television signal comprises also at lease one calculation block connected to the signal inputs and operating with fuzzy logic. The calculation block is capable of executing a switch between at least two different interpolation procedures, to wit interfield and intrafield.
    Type: Grant
    Filed: April 21, 1995
    Date of Patent: April 8, 1997
    Assignees: SGS-Thomson Microelectronics S.r.l., Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Massimo Mancuso, Rinaldo Poluzzi, Gianguido Rizzotto
  • Control circuit for setting a bias source at partial stand-by
    Patent number: 5619160
    Abstract: The invention relates to a control circuit for setting a .DELTA.Vbe/R bias source at stand-by from a stand-by control signal including circuitry for virtually modifying, as a function of the state of the stand-by control signal, the emitter surface area of at least one of the matching-pair current mirror bipolar transistors in the bias source.
    Type: Grant
    Filed: June 22, 1995
    Date of Patent: April 8, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Philippe Sirito-Olivier, Bernard Majoux
  • Regulation circuit and method for the erasing phase of non-volatile memory cells
    Patent number: 5617356
    Abstract: A regulating circuit for discharging non-volatile memory cells in an electrically programmable memory device, of the type which comprises at least one switch connected between a programming voltage reference and a line shared by the source terminals of the transistors forming said memory cells, and at least one discharge connection between said common line to the source terminals and a ground voltage reference, further comprises a second connection to ground of the line in which a current generator is connected and a normally open switch. Also provided is a logic circuit connected to the line to compare the voltage value present on the latter with a predetermined value, and to output a control signal for causing the switch to make. This solution allows a slow discharging phase of the line to be effected at the end of the erasing phase.
    Type: Grant
    Filed: February 21, 1995
    Date of Patent: April 1, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Carla Golla, Silvia Padoan, Marco Olivo
  • Power semiconductor devices
    Patent number: 5616512
    Abstract: A process for manufacturing integrated circuits includes the following steps. First, an oxide layer is formed on at least one surface of two respective semiconductor material wafers. Next, a single semiconductor material wafer is obtained with a first layer and a second layer of semiconductor material and a buried oxide layer interposed therebetween starting from said two semiconductor material wafers by direct bonding of the oxide layers previously grown. The single wafer is submitted to a controlled reduction of the thickness of the first layer of semiconductor material and the top surface of the first layer of semiconductor material is lapped. Dopant impurities are selectively introduced into selected regions of the first layer of semiconductor material to form the desired integrated components.
    Type: Grant
    Filed: December 21, 1994
    Date of Patent: April 1, 1997
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventor: Cesare Ronsisvalle
  • Time delayed filter monolithically integratable
    Patent number: 5614858
    Abstract: A time delay filter includes at least one field-effect transistor of the MOS type and at least one bipolar transistor having their respective base and gate terminals connected together. The bipolar transistor is coupled to an input terminal through a drive transistor, and the field-effect transistor is coupled to an output terminal. The charge time for the gate capacitance of the field-effect transistor, using the low base current of the bipolar transistor, enables high-frequency noise to be filtered out of input digital signals.
    Type: Grant
    Filed: January 12, 1994
    Date of Patent: March 25, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Alessio Pennisi
  • Circuit for computing membership function values in a fuzzy logic controller
    Patent number: 5615303
    Abstract: Circuit for calculation of values of membership functions in a controller operating with fuzzy logic procedures. The membership functions are of triangular or trapezoidal form and are defined in a so-called discourse universe discretized in a finite number of points. The controller includes a central control unit equipped with a memory section for storage of said membership functions, a microprocessor, and an interface. The membership functions are stored by means of a codification of the coordinate of the vertex and the slopes at the sides of the vertex. The circuit includes a calculator connected to the memory section, the microprocessor, and the interface, to determine the value of each membership functions at each point of the discourse universe using the stored vertex and slopes.
    Type: Grant
    Filed: March 21, 1995
    Date of Patent: March 25, 1997
    Assignee: Consorzio per la Ricerca sulla Microelettronica nel Mezzogiorno
    Inventors: Massimo Abruzzese, Biagio Giacalone
  • Circuit for inverting elements of a finite field
    Patent number: 5612910
    Abstract: A circuit for inverting a number of n bits of a finite field of 2.sup.n =N+1 elements comprises a first circuit for raising to the power t=2.sup.n/2 receiving the number to invert. A first complete multiplier receives the number to invert and the output of the circuit for raising to the power t. A second circuit provides the product of the output of the circuit for raising to the power t and the inverse of the output of the first complete multiplier.
    Type: Grant
    Filed: July 13, 1995
    Date of Patent: March 18, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jacques Meyer
  • Method for the fast charging of a battery and integrated circuit for the implementation of this method
    Patent number: 5612607
    Abstract: To carry out a fast charging of a battery, a high current is injected into this battery while, at the same time, the terminals of this battery are monitored. This injection is stopped when this voltage undergoes an inflection of its variation. It is shown that, given the security of the system, it is possible to charge nickel-cadmium or nickel-metal-hydride type batteries with currents that are even higher than in prior systems.
    Type: Grant
    Filed: March 18, 1994
    Date of Patent: March 18, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Jean Nicolai
  • Switching regulator with dyssymetrical differential input stage
    Patent number: 5612611
    Abstract: A voltage regulator circuit having one input to receive a voltage to be limited, this input being connected to a ground by means of a limiting transistor. To control this transistor, a comparator and a dissymetrical differential stage are used. The differential stage receives the voltage to be limited and a reference voltage produced by means of a Zener diode, and supplies the comparator with voltages lower than those that it receives. The output of the comparator is connected to the control gate of the limiting transistor. This regulator circuit can advantageously be used to regulate a voltage produced by a voltage multiplier within an electrically programmable memory.
    Type: Grant
    Filed: April 19, 1995
    Date of Patent: March 18, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Sylvie Drouot, Gerard D. F. Silvestre
  • Semiconductor component for supplying, recirculating and demagnetizing an inductive load
    Patent number: 5612562
    Abstract: A semiconductor component for switching an inductive load, comprises first and second external terminals, first and second control terminals and a node. A vertical bipolar transistor has a base region and is disposed between the first external terminal and the node. A first vertical transistor is disposed between the node and the second external terminal. A zener diode and a second vertical transistor are connected parallel between the base and the node.
    Type: Grant
    Filed: September 14, 1995
    Date of Patent: March 18, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventors: Jean-Louis Siaudeau, Antoine Pavlin
  • Circuit for covering initial conditions when starting-up an integrated circuit device
    Patent number: 5612641
    Abstract: A circuit for resetting initial conditions upon starting of an integrated circuit device has null current consumption under normal operating conditions. The circuit includes an input stage, which is a threshold circuit, and pilots through an input node an output stage which is a trigger circuit with hysteresis. The input node of the output stage is connected to ground through a condenser and is connected through a transistor to a connection node between a condenser and a diode connected transistor which are inserted between the power supply and ground. The gate terminal of the first transistor is grounded.
    Type: Grant
    Filed: January 30, 1995
    Date of Patent: March 18, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventor: Mauro L. Sali
  • Voltage reference circuit
    Patent number: 5610506
    Abstract: A reference circuit is provided which generates a reference voltage which is always at least as high as a stable reference value. This is done by generating a lock signal which is maintained at a first logic level during start-up of the reference circuit and then attains a second logic level when the reference value has stabilized. The reference circuit can be a bandgap reference circuit.
    Type: Grant
    Filed: November 15, 1995
    Date of Patent: March 11, 1997
    Assignee: SGS-Thomson Microelectronics Limited
    Inventor: David H. McIntyre
  • Integrated circuit memory with column voltage holding circuit
    Patent number: 5610860
    Abstract: An integrated circuit memory comprises a circuit that keeps the column voltage constant during the recording of a binary value. This circuit has a differential amplifier which measures the difference between a reference voltage given by a voltage divider and a voltage representative of the bit line. This amplifier gives a signal that is applied to the gate of a transistor of the column-addressing circuit.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: March 11, 1997
    Assignee: SGS-Thomson Microelectronics S.A.
    Inventor: Olivier Rouy
  • Circuital arrangement for preventing latchup in transistors with insulated collectors
    Patent number: RE35486
    Abstract: A circuital arrangement which comprises a vertical PNP transistor with insulated collector, which has a P-type collector structure surrounded by an N-type well and forms a junction therewith.
    Type: Grant
    Filed: February 9, 1995
    Date of Patent: April 1, 1997
    Assignee: SGS-Thomson Microelectronics S.r.l.
    Inventors: Franco Bertotti, Paolo Ferrari