Abstract: A voltage-controlled power monolithic bidirectional switch has two main terminals and includes a control electrode whose voltage is referenced to one of the main terminals. The switch includes a lateral P-channel MOS transistor; a vertical N-channel MOS transistor, the source well of the vertical N-channel MOS transistor also constituting the source of the lateral transistor; a lateral thyristor whose first three regions correspond to the source, drain and channel of the lateral MOS transistor; a first vertical thyristor disposed in parallel with the lateral thyristor; and a second vertical thyristor having a polarity opposite to the first polarity and disposed in parallel with the vertical MOS transistor.

Abstract: A semiconductor device is described, incorporating electron traps at the interface between a semiconductor substrate and a gate dielectric layer of an insulated gate field effect transistor, such device being capable of retaining charge in the electron traps for a certain time, allowing volatile memory circuits to be produced wherein each cell occupies only the area required for a single transistor.

Abstract: A digital circuit for controlling the gain of an amplifier stage of a coded signal receiving channel is provided. The circuit includes a peak detector coupled to the input terminal of the receiving channel through a coded signal rectifying circuit and a gain control stage. The gain control stage includes a digital comparator having two input terminals respectively connected to an output terminal of the peak detector and to a memory, and an output terminal coupled to a gain control terminal of the amplifier stage. The address selectable contents of the memory contain predetermined peak values in coded form.

Abstract: The disclosure relates to memories in integrated circuit form. A programmable non-volatile memory cell of the bistable type is described. This memory cell can take one stable state or another depending on whether either one of two floating-gate transistors of the cell has been programmed. In the initial state, neither of the two transistors is programmed so that the cell cannot remain in this state and at least one of the transistors has to be programmed. To avoid this, there is provided an additional transistor controlled by the output of the cell to set up imbalance in the cell which can then take a well-determined stable state even if no transistor is programmed, while at the same time ensuring that there is no consumption of current by the cell even in this case. The disclosure can be applied to the redundancy circuits of large-capacity memories to memorize the defective addresses. It makes it possible to avoid having to program the cells when the memory has no defective addresses.

Abstract: A method employing a test structure identical to the memory array whose gate oxide or interpoly dielectric quality is to be determined, except for the fact that the cells are connected electrically parallel to one another. The test structure is subjected to electrical stress of such a value and polarity as to extract electrons from the floating gate of the defective-gate-oxide or defective-interpoly-dielectric cells and so modify the characteristic of the cell while leaving the charge of the non-defective cells unchanged. In this way, only the threshold of the defective cells is altered. A subthreshold voltage is then applied to the test structure, and the drain current through the cells, which is related to the presence of at least one defective cell in the structure, is measured. Measurement and analysis of the current-voltage characteristic provides for determining the number of defective cells.

Abstract: To prompt a repairing operation as and when defective cells appear in an integrated circuit memory, there is provided an auxiliary memory related to a programmable comparator. Whenever the cells of the memory are to be read, the auxiliary memory is read and its content is compared with the address selected in the memory array. The result of this comparison produces, in real time, the addressing signals of a redundant cell and signals for the neutralization of the initially encountered cell. This system can be used more particularly in the field of EEPROM type memories.

Abstract: A pair of masks is designed to expose an upper surface and a lower surface of a silicon wafer. Each mask includes, outside its operative surface area, corresponding to the surface of the silicon wafer, identical or complementary sighting marks.

Abstract: A three-phase alternator protection component is associated with a rectifying bridge. Three Shockley diodes and an avalanche diode are interconnected through three electrodes, of a first polarity, of the Shockley diodes, and the electrode, of the opposite polarity, of the avalanche diode to a common terminal that is connected to the output terminal, having a first polarity, of the rectifier. Each second electrode of the Shockley diodes is connected to each output of the alternator, and the second terminal of the avalanche diode is connected to the second output terminal of the rectifier.

Abstract: A device for mounting chips between two flat heat sinks includes a base provided with an assembly of ramps disposed in a saw-tooth pattern; a plurality of main stops aligned at the bottom of the ramps and open in a direction toward the top of the ramps; and, for each main stop, a median stop protruding from the main stop and dividing it into two sub-stops, each sub-vee for receiving a heat sink disposed in parallel with the associated ramp, the median stop being designed to accommodate a chip.

Abstract: A PIC structure comprises a lightly doped semiconductor layer of a first conductivity type, superimposed over a heavily doped semiconductor substrate of the first conductivity type, wherein a power stage and a driving and control circuitry including first conductivity type-channel MOSFETs and second conductivity type-channel MOSFETs are integrated; the first conductivity type-channel and the second conductivity type-channel MOSFETs are provided inside second conductivity type and first conductivity type well regions, respectively, which are included in at least one isolated lightly doped region of the first conductivity type completely surrounded and isolated from the lightly doped layer of the first conductivity type by means of a respective isolation region of a second conductivity type.

Abstract: Device for limiting the working voltage for mechanical switches in telephony includes terminals for connection to a telephone line, a connection and power supply branch for a control circuit extending from a first terminal, the branch having a first switch, the cathode terminal of a first Zener diode and the source terminal of a first MOSFET transistor being connected to the output terminal of the first switch, the gate terminal of the first MOSFET transistor being connected, through the anode terminal of the Zener diode, to the first terminal. The current absorbed by the device may be adjusted.

Abstract: A method for testing an electrically programmable non-volatile memory including a cell matrix and an internal state machine which governs the succession and timing of the memory programming phases includes excluding the internal state machine, modifying at least one of the control signals to program the cell matrix, and verifying programming correctness.

Abstract: A processor architecture for executing a current task among a plurality of possible tasks. The architecture includes: a plurality of instruction pointers respectively associated with the tasks and each storing the address of the current instruction to be executed of the associated task, only one of these pointers being enabled at a time to supply an address to the memory; a priority level decoder including circuitry for assigning a predetermined priority level to each request signal and for enabling the instruction pointer associated with the active request signal having the highest priority level; and a mechanism for incrementing the content of the enabled instruction pointer and for reinitializing it at the start address of the associated program when its content reaches the end address of the associated program.

Abstract: A half-latch for a scan latch is described. The half-latch has an input terminal for receiving an input signal a first control terminal for receiving a clock signal and an output terminal. When enabled, the half-latch adopts a data transfer state in which it transmits a signal from its input terminal to its output terminal. Alternatively, the half-latch can adopt a data holding state in which a signal is stored on the output terminal, these states being selected in dependence on the state of the clock signal. The half-latch described herein has a second control terminal which receives the control signal to selectively disable the half-latch. This allows a common clock signal to be used when a scan latch is constructed using these half-latches.

Abstract: An a.c. switch includes across first and second main terminals a first thyristor disposed in parallel with, but in an opposite direction of, a first diode and in series with a second thyristor disposed in parallel with but in an opposite direction of, a second diode. The first thyristor has a gate terminal connected to its gate area. The second thyristor and second diode are vertically realized in the same substrate, their conduction areas being closely interlaced, whereby a polarity inversion following a conduction period of the second diode causes the second thyristor to become conductive.

Abstract: An integrated circuit memory organized in rows and columns of memory cells and having a plurality of redundancy fuses for storing an address of defective rows and columns of the memory cells, in the redundancy fuses, and for selecting a replacement redundant element when an address of a defective row or column is detected. The address code of each defective row or column is recorded in a column of redundancy fuses, each row of the column comprising two cells per digit of the address code, each cell being responsive to either the digit itself or its complement. During a reading of the integrated circuit, only the column that corresponds to the previously recorded address code will not be characterized by a current flow and will be selected as the associated redundant element.

Abstract: The input signal is filtered using at least two filtering operations (i.e. at least two types of transfer functions), and then is reconstituted by summing the two different digital outputs generated by each filtering arrangement, for example by using a summing circuit. In a preferred embodiment of the invention, a single programmable filter processor is used and is operated in two alternately selected modes, each sharing common filter coefficients. A clock signal alternately selects the two filtering modes. The subsequent outputs from a first mode are delayed and then added to the output of the second mode to produce the desired output signal.

Abstract: The invention relates to charge-pump circuits used for the generation, in an integrated circuit, of an internal supply voltage Vpp which is considerably greater than the external supply voltage Vcc. In a charge pump configuration with capacitors and transistors, certain transistors must be driven by bootstrapped logic signals, i.e., having a logic level which is greater than Vcc in order to overcome the threshold voltage of the transistors. According to the invention, there is an oscillator followed by a phase splitter stage which is in turn followed by a bootstrap amplifier stage. The oscillator is a ring oscillator having a number of logic gates which is as small as possible, preferably only three. A satisfactory frequency stability of the charge pump is thus obtained and therefore its design is made easier and its adaptability to various electronic circuits is improved.

Abstract: An integrated structure pad assembly for wire bonding to a power semiconductor device chip including a chip portion having a top surface covered by a metallization layer which has a first sub-portion wherein functionally active elements of the power device are present. The chip portion has at least one second sub-portion wherein no functionally active elements of the power device are present. The top surface of the at least one second sub-portion is elevated with respect to the first sub-portion to form at least one protrusion which forms a support surface for a wire.

Abstract: An electronic comparator circuit having a high speed during switch phase and combining the advantages of bipolar technology with those of CMOS technology. The circuit consists of a differential stage input circuit having a differential pair of bipolar transistors forming its outputs. The output stage contains a pair of MOS transistors having gate electrodes in common. The pair of MOS transistors is connected on one side to the outputs of the input portion and on the other side to a positive supply pole via a current mirror circuit. The output contains another pair of MOS transistors with gate electrodes in common connected between the out puts of the input portion and ground. The drain electrode of the first pair of MOS transistors forms the output for the comparator.