Abstract: Apparatus for repeatedly generating a staircase ramp voltage pulse on a bus connected to a capacitive load employing a set of DC voltage sources, each producing a voltage of a step in the staircase ramp voltage. A storage capacitor is connected between the output terminal of each voltage source and ground. An FET switch is connected between each of the output terminals and the bus and between ground and the bus. A timing circuit closes each of the FET switches in order to produce a staircase ramp voltage on the bus charging the capacitive load. When it is desired to discharge the capacitive load, the timing circuit then closes the switches in reverse order. Each storage capacitor is charged by the discharging capacitive load to a voltage above the voltage of its associated voltage source. The energy thus stored is used during the next cycle to contribute to the energy required to charge the capacitive load on the bus.

Abstract: Junction field effect transistor and method of fabrication. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. A layer of silicon dioxide is grown on the surface of the epitaxial layer and selectively removed to expose silicon in a pattern of a plurality of parallel surface areas with parallel strips of silicon dioxide in between. A second epitaxial layer is deposited over the exposed surface areas and the strips of silicon dioxide. Barriers of silicon dioxide are formed in the second epitaxial layer extending from the surface to adjacent to but spaced from the edges of the buried strips. P-type conductivity imparting material is implanted and then diffused into the zones of the second epitaxial layer defined by adjacent barriers and overlying the buried strips to form gate regions.

Abstract: Ion implanted polydiacetylenes prepared by implanting ions into substituted polydiacetylenes at fluence levels from about 1.times.10.sup.13 ions/cm.sup.2 to about 1.times.10.sup.17 ions/cm.sup.2 are disclosed. Ion implanted polydiacetylenes exhibit electrical and/or optical properties which are different from those of untreated polydiacetylenes.

Abstract: A high-gain, high-frequency, high-power, push-pull amplifier employing a pair of static induction transistors (SIT's) in common-source configuration. A pair of capacitances each of approximately the same capacitive value as the drain-to-gate parasitic feedback capacitance of each SIT are cross-coupled between the drains and gates of the pair of SIT's to neutralize the drain-to-gate capacitances and provide stable operation.

Abstract: Compositions based on polypyrrole are described having incorporated therein a polyether, such as polytetrahydrofuran. The polyether is present in an amount of at least about 10 weight percent of the polypyrrole present. The compositions exhibit improved processing properties over these of polypyrrole. A process for producing the compositions is also described in which a pyrrole compound is electrochemically polymerized in the presence of a dissolved polyether.

Abstract: Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.

Abstract: Method of producing two-layer metal interconnections in a semiconductor integrated circuit structure coated with silicon dioxide. Masking material is deposited on the silicon dioxide. Openings are formed in the masking material and then in the silicon dioxide to expose contact areas on the integrated circuit structure. A first metal, tungsten, is deposited on the masking material and on the contact areas exposed at the openings. The masking material and the overlying tungsten are stripped off leaving tungsten only on the contact areas. A second metal, aluminum, is deposited over the silicon dioxide and the tungsten on the contact areas. Aluminum is selectively removed to form a pattern of conductive members of tungsten-aluminum on the contact areas and of aluminum over the silicon dioxide.

Abstract: Method of producing a silicon structure for fabricating integrated circuit devices therein by forming a plurality of regions of N-type single crystal silicon of high resistivity inset in the surface of silicon of either P-type conductivity or of N-type conductivity of low resistivity. The silicon contiguous with the regions of high resistivity N-type silicon is converted to porous silicon by anodically treating in an aqueous solution of HF. Then, conductivity type imparting material is diffused through the porous silicon into portions of the regions of N-type conductivity to alter their electrical characteristics to P-type or to low resistivity N-type. The porous silicon is then oxidized to silicon oxide, electrically isolating each of the N-type regions and its associated portion.

Abstract: Junction field effect transistor, specifically a static induction transistor, and method of fabricating. An epitaxial layer of high resistivity N-type silicon is grown on a substrate of low resistivity silicon. The surface of the epitaxial layer is coated with silicon nitride, portions of the silicon nitride are removed, and the silicon is etched to form parallel grooves with interposed ridges of silicon. A layer of silicon nitride is applied and then removed except from the side walls of the grooves. Exposed silicon at the bottoms of the grooves is converted to silicon dioxide to build up layers of silicon dioxide in the grooves. The remaining silicon nitride is removed. P-type conductivity imparting material is ion implanted into alternate (gate) ridges and diffused to form gate regions which extend laterally beneath the silicon dioxide in the adjacent grooves. N-type conductivity imparting material is ion implanted in the top of the intervening (source) ridges.

Abstract: Apparatus employing a light beam to affect another light beam. A primary beam of linearly polarized monochromatic light is directed on an element of chromium chalcogenide spinel magnetic semiconductor, specifically single crystal CdCr.sub.2 Se.sub.4. A control beam of monochromatic light is selectively elliptically polarized and directed at the element. As the light beams traverse the same path through the element the circularly polarized control beam interacts with the element thereby changing the effect of the element on the linearly polarized primary beam to rotate the plane of linear polarization of the primary beam. A linear polarization analyzer receives the primary beam from the element and passes, blocks, or diverts light depending upon the plane of linear polarization of the incident light.

Abstract: Method of fabricating a monolithic integrated circuit structure incorporating a complementary pair of GaAs/AlGaAs modulation-doped field effect transistors (MODFET's) including providing a substrate of semi-insulating GaAs, depositing an epitaxial layer of undoped AlGaAs on its surface, and ion-implanting a heavily doped N-type donor region and a heavily doped P-type acceptor region in the undoped AlGaAs. A thin spacer layer of undoped AlGaAs is epitaxially deposited on the previously deposited AlGaAs layer, and an epitaxial layer of undoped GaAs is deposited on the spacer layer. First and second gate members which form Schottky barriers with the GaAs are placed on the GaAs layer overlying portions of the N-type donor region and P-type acceptor region, respectively. N-type source and drain zones are formed in the GaAs layer on opposite sides of the first gate member, and P-type source and drain zones are formed in the GaAs layer on opposite sides of the second gate member.

Abstract: A 3 dB quadrature coupler is connected to an RF input terminal and an LO input terminal, and its outputs are connected to first and second antiphase power dividers. The outputs of the first and second antiphase power dividers are individually connected to the gates of four field effect transistors (FET's). The drains of two of the FET's are connected together and to a low pass filter, and the drains of the other two FET's are connected together and to a second low pass filter. The outputs of the filters are connected to the two inputs of a differential amplifier, and the IF signal is taken at the output of the differential amplifier.

Abstract: A first 3 dB quadrature coupler is connected to an RF input terminal and its outputs are connected to first and second antiphase power dividers. The outputs of the first and second antiphase power dividers are individually connected to the first gate of four dual-gate field effect transistors (FET's). A second 3 dB quadrature coupler is connected to an LO input terminal and its outputs are connected to third and fourth antiphase power dividers. The outputs of the third and fourth antiphase power dividers are individually connected to the second gates of the four FET's. The drains of two of the FET's are connected together and to a low pass filter, and the drains of the other two FET's are connected together and to a second low pass filter. The outputs of the filters are connected to the two inputs of a differential amplifier, and the IF signal is taken at the output of the differential amplifier.

Abstract: Energy source of a low power high frequency oscillator section driving a high power high gain amplifier section. The amplifier section includes one or more SIT's. The dc operating potential is applied to the drain electrode of one of the SIT's and is supplied to the other through a dc path from the source electrode of the one SIT to the drain electrode of the other. Operating potential from the dc biasing network between the source and gate electrode of an SIT in the amplifier section is conducted through a dc path to a transistor in the oscillator section to provide operating power for the oscillator section. The oscillator output is connected through a high frequency coupling dc blocking path to the amplifier input to provide a drive signal to be amplified and extracted at the amplifier output.

Abstract: A counter/divider apparatus employing an array of counters arranged in parallel. Each counter repeatedly counts through a sequence of a number of clock pulses. The number is different for each counter and the numbers are relatively prime numbers. The outputs of the counters are applied to a detector that recognizes a preset combination of output signals which is present after a predetermined number of clock pulses have been received. The detector then produces an output pulse which clears all the counters to their initial states, and the cycle is repeated. The apparatus thus divides the input clock pulses by the aforementioned predetermined number.

Abstract: Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.

Abstract: A power source consisting of a low power high frequency oscillator section driving a high power high gain amplifier section. The amplifier section includes one or more SIT's. The dc operating potential is applied to the drain electrode of one of the SIT's and is supplied to the other through a dc path from the source electrode of the one SIT to the drain electrode of the other. Operating potential from the dc biasing network between the gate and source electrodes of an SIT in the amplifier section is conducted through a dc path to a transistor in the oscillator section to provide operating power for the oscillator section. The oscillator output is connected through a high frequency coupling dc blocking path to the amplifier input to provide a drive signal to be amplified and extracted at the amplifier output.

Abstract: High voltage, high frequency amplifier employing power transistors. The amplifier provides parallel ac signal amplification paths through each transistor and a single dc power path through the transistors in series. In one embodiment two FET's have their gate electrodes connected to an input terminal and their drain electrodes connected to an output terminal so as to provide two parallel ac amplifying paths while blocking dc current flow. The drain electrode of the first FET is connected through an RF choke to a source of dc operating potential, and its source electrode is connected through an RF choke to the drain electrode of the second FET. The source electrode of the second FET is connected to ground through a zener diode. A single dc conductive path is thus provided between the source of operating potential and ground through the two FET's in series.

Abstract: High voltage, high frequency amplifier employing power transistors. The amplifier provides parallel ac signal amplification paths through each transistor and a single dc power path through the transistors in series. In one embodiment two FET's have their source electrodes connected to an input terminal and their drain electrodes connected to an output terminal so as to provide two parallel ac amplifying paths while blocking dc current flow. The drain electrode of the first FET is connected through an RF choke to source of dc operating potential, and its source electrode is connected through an RF choke to the drain electrode of the second FET. The gate electrode of the second FET is connected to ground. A single dc conductive path is thus provided between the source of operating potential and ground through the two FET's in series.

Abstract: Disclosed is a method for applying a continuous protective coating to the surface of individual phosphor particles. The method involves chemical vapor deposition of the protective coating on individual particles of a phosphor powder while the phosphor particles are suspended in a fluidized bed. During the method, the fluidized particles are exposed to the vaporized coating precursor material at a first temperature, which is less than the decomposition temperature of the precursor material, and the precursor material is reacted to form the desired coating material at a second temperature, which is greater than or equal to the temperature at which the precursor material reacts to form the coating material.