Abstract: In accordance with the present invention, an apparatus includes a system bus having memory bank identification signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank, and at least one commander module. The commander module contains decode logic which includes memory mapping registers associated with unique values to be driven on the memory bank identification signals. The memory banks contain compare logic including a virtual node identification register which stores a predetermined value to be compared with the value driven on the memory bank identification signals to determine if the memory bank is the target of the current transaction. Thus, memory banks need not decode the entire system bus address to determine if they are the target of the transaction which reduces the time required to complete a transaction with memory.

Abstract: A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency.

Abstract: A language construct that allows a software programmer to use an intermediate or high-level language command to explicitly group operations or fuse loops in a group of statements operating on parallel arrays is disclosed. The command instructs a compiler, which would otherwise add temporary variables to avoid data dependencies or perform data dependency analysis, to translate the enclosed statements directly into machine language code without adding those temporary variables and without performing any data dependency analysis. Execution of the command results in the performance of the group of statements by all of the virtual processors.

Abstract: Modern database systems provide media recovery by taking periodic backups and applying a transaction log to the backup to bring the data up-to-date. A multi-versioned database is one that retains and provides access to historical versions of data. The present invention shows how a history database, supported by the Time-Split B-tree, can be used to also provide the backup function of media recovery. Thus, the same versions used for database history are used for database backup. The cost of taking a backup is comparable to the cost of a good differential backup method, whereby only changed data is backed up. The media recovery cost, especially when the media failure is only partial, e.g., a single disk page, will frequently be lower.

Abstract: An integrated circuit handling, packaging and testing apparatus in the form of a testable chip carrier comprising a rigid substrate onto which a chip may be bonded, and which provides a high density interconnect pattern orthogonally aligned to the chip bond pads for wire bonding thereto. The interconnect also provides external bonding points patterned for similar orthogonal alignment to the external device to which the chip is to be connected, and the dimensions of the carrier are substantially smaller than an equivalent standard or custom package type. A hermetic or non-hermetic seal lidding operation may be carried out on the chip and carrier. The carrier also provides a detachable test perimeter allowing full-functional testing and burn-in of the attached wire-bonded chip prior to placement on a printed circuit board or multi-chip module.

Abstract: An apparatus for dithering an input image to produce an output array for representation on an output device is described. The apparatus includes an input device to store input image pixels having a first plurality of chrominance or luminance levels; a dithering system including a dither template including an M by N matrix of integer threshold values, the uniform distribution of threshold values throughout the dither template possessing homogeneous attributes. The apparatus further includes a normalizer unit for normalizing the threshold values of the dither template for storage in a dither matrix according to the first plurality of chrominance or luminance levels of the input image pixels and a second plurality of chrominance or luminance levels of the output array and a summation unit to add the input image pixel chrominance or luminance values to the normalized threshold values of the dither matrix.

Abstract: A method and apparatus of remotely booting a target computer system from a host computer system over a communication medium comprises exchanging messages between the host and target computer systems. The host computer system controls the remote booting and communicates the initial booting request to the target computer system. The target computer system may respond by communicating to the host computer system whether it will boot. During booting, the target computer system transitions between a polling or stopped state and an interrupt-driven state by transitioning both a target operating system and network hardware in the target computer system between the polling and interrupt-driven states.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination Circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: An operator of a digital computer system issues a series of operational commands to respective concurrently executing application programs. Each application program includes a client executive routine that records the application program's operational commands and an associated time stamp indicating when the operational command was received from the operator. The operational commands and the time stamps are transferred to a core executive program that records a script of the operational commands. The core executive determines from the time stamps a global sequence in which the operator issued the operational commands to the application programs. In a playback mode, the computer system re-executes the application programs by issuing the operational commands from the script memory to the application programs in the determined global sequence. In a preferred embodiment, the core executive determines a sequence identifier for each operational command.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: It is not always possible or practical to fully translate an original computer program because execution transfer instructions may have computed destination addresses that cannot be determined until program execution. Instead, a digital computer alternately executes a translated program that is a partial translation of the original computer program, and interprets the original program. When execution of the translated program specifies a transfer to an untranslated portion of the original program, execution is transferred to an interpreter to interpret the original program. When interpretation of the original program reaches a portion of the original program having been translated, execution is transferred to the translated program. In a preferred embodiment, the original program is partially translated by automatically generating a flowgraph, and using the flowgraph to analyze the program to provide information about blocks of instructions in the flowgraph.

Abstract: A system is provided for executing and debugging multiple codes in a multi-architecture environment that includes a real X architecture (domain) and a simulated (Y) architecture (domain). The multiple code executing and debugging system comprises an X computer system having a memory with stored X and Y code and having the X architecture embodied therein.A detector is provided to detect calls from executing code in either domain for cross-domain services including execution of cross-domain routines. A jacketing system jackets cross-domain routine calls to interface the calling conventions of the calling and the called routines.

Abstract: A software unit development and test methodology in which a software application or project is dividing into conceptual units. Each unit is first developed and debugged in an isolated testing environment which simulates the actual testing environment through test conditions. Following unit testing, other tested units are incrementally combined and tested in a similar isolated manner. Automatic generation of a testing environment and development system driving debugging and testing software, for measuring testing completeness, and for verifying correctness of future development and maintenance efforts are provided.

Abstract: In a method for improving a circuit having a logically false path through static analysis of a software model, a computer receives information describing the false path, determines a true path alternate to the false path, and analyses the circuit model with respect to the true path.

Abstract: A program is translated by automatically generating a flowgraph, using the flowgraph to analyze the program to provide information about blocks of instructions in the flowgraph, and then using the flowgraph and the information about the blocks of instructions to generate translated instructions. Due to execution transfers to computed destination addresses that are not determined prior to program execution, it is not possible to include all of the program instructions in the flowgraph. Execution transfers to these computed destinations are coded as calls to an interpreter that interprets the untranslated code. Returns are made from the interpreter to block entry points that are the first instructions in the blocks. Moreover, information about the location of untranslated instructions in an original program is discovered during execution of a partial translation of the program, and that information is used later during retranslation of the original program.

Abstract: The method for efficiently providing an optimized fanout network includes the steps of providing a series chain of inverters for driving a number of loads. Each load is assigned to a given location of the inverter chain according to the polarity and the required time of the load. Tree-covering techniques are used in conjunction with dynamic programming to minimize the total area of the fanout chain by selecting and sizing the gates to be used in the fanout chain. With such an arrangement, a minimal area fanout chain which satisfies the timing constraints of each load is provided.

Abstract: A termination device including a package having a first plurality of pins and a plurality of resistors disposed in the package is described. Each resistor has a pair of termini with one of the termini of each resistor connected to a corresponding one of the first plurality of pins and the other termini connected to a common conductor. The device also includes a reference conductor connected to a mid-portion of the common conductor and to a pin of the package. An alternate embodiment of the termination device includes two reference conductors connected to respective end portions of the common conductor and to pins of the package.

Abstract: A system or method is provided for translating a first program code to a second program code and for executing the second program code while preserving instruction state-atomicity of the first code. The first program code is executable on a computer having a first architecture adapted to a first instruction set and the second program code is executable on a computer having a memory and register state and a second architecture adapted to a second instruction set that is reduced relative to the first instruction set.A first computer translates the first code instructions to corresponding second code instructions in accordance with a pattern code that defines first code instructions in terms of second code instructions.

Abstract: Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine in the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of a eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handing routine if the semaphore indicates that an exception occurred when the speculative instruction was executed, and the predicate is true, which indicates that the speculative instruction was properly executed.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.