Abstract: A CMOS device is provided having a high concentration of nitrogen atoms at the SiO.sub.2 /Si interface reducing hot carrier effects associated with operating shorter devices at voltage levels typically used with longer devices. In one embodiment, the process for providing the CMOS device resistant to hot carrier effects makes use of a sacrificial oxide layer through which the nitrogen atoms are implanted and is then removed. Following removal of the sacrificial oxide layer, a gate oxide is grown giving a CMOS device having high nitrogen concentration at the SiO.sub.2 /Si interface. In an alternate embodiment, nitrogen atoms are implanted through the final gate oxide using an implantation energy which does not damage the oxide layer.

Abstract: Lock management in a distributed data sharing computer system in which resources are shared by servers having local lock managers and the computer system having a global lock manager. Lock modes are defined to govern the availability of resources to the servers, including defining at least one lock mode that conflicts with at least another of the lock modes without covering any locks associated with the lock modes. Locks indicative of a specific lock mode are assigned to the resources. Requests for access to the resources are administered by a local lock manager associated with the requesting server without exposing the lock modes associated with the locks on the resources to the global lock manager unless the requests for access relate to a resource that is not covered by a lock assigned by the global lock manager.

Abstract: An apparatus for providing data to an I/O bus at the maximum I/O bus bandwidth comprises an exerciser unit coupled to the I/O device. The exerciser unit includes DMA circuitry for providing a constant stream of transactions to the I/O bus. Each transaction provides a plurality of data quadwords to the I/O bus which are parity protected. The exerciser unit includes a memory device for storing data to be provided for each transaction, and a parity circuit for calculating and providing parity for the data stored in the memory. The exerciser unit further includes a data generation device for providing both data having predictable parity and the parity to the bus for each bus cycle while bypassing the parity generation logic to provide data at maximum bandwidth. The data generation device provides a sequence of different data bytes using a modified Gray-code algorithm, which facilitates parity generation for each byte in the sequence of bytes.

Abstract: An apparatus and method for transferring data via DMA in data processing system from a host system to a transmission network. The transferred data is in longword format in which each longword consists of four bytes. Within a longword, valid bytes intended for transmission are contiguous. The adapter or I/O device includes a packet memory and a FIFO circuit interposed between the host system and packet memory to allow for differences in access speed of a host memory and the packet memory. The FIFO circuit contains four discrete FIFO circuits that are separately addressable for writing the bytes of each longword received from the host memory for storage in the FIFO circuit. The received longword is applied to a barrel shifter which aligns the first valid byte in the received longword with the one of the four discrete FIFO circuits containing a first available storage location at a current FIFO longword address.

Abstract: In a lossless compression algorithm, the left most point of a current interval, i.e., the code point is updated by using a code point updating device which handles inputs identified by R and X, and uses two registers. The first of the two register is an interval width register, and the second is a code point register. The updating device comprises a grid of n.times.n cells chosen from four basic component cells, i.e.,(i) above diagonal cells designated "ad" and located above the principal diagonal of the grid,(ii) diagonal cells designated "d" and located on the principal diagonal, incorporating and adder (31) and a multiplexer (30) and at least one register (32);(iii) a single cell designated "fd" for "final diagonal", located at the bottom end of the diagonal and incorporating an adder (31) a multiplexer (30) and at least one register (32), and(iv) output retiming cells designated "or", incorporating a register (35).

Abstract: A method of testing an integrated circuit design includes the steps of providing a logical model of an integrated circuit, having a plurality of data ports, providing at least two simulators, the first simulator coupled to a first data port of the integrated circuit model, and the second simulator coupled to a second different data ports of said integrated circuit model. The further includes the steps of providing an instruction stream to the first and second simulators, the instruction stream including at least two instruction threads corresponding to the at least two simulators, the simulators providing signals to the data ports in accordance with instructions provided from each of the instruction threads. In addition, the method further includes the step of delaying the first simulator from processing its corresponding instruction thread until dependencies between instruction threads have been satisfied.

Abstract: A data processing system includes a plurality of nodes connected to a shared data path, one of said plurality of nodes being a commander node to initiate a transaction on said shared data path, and one of said plurality of nodes being a responder node. The system also includes means for providing, by said responder node, a response to said commander node indicating unavailability of said responder node and for providing an acknowledgement of said transaction over said shared data path; and means, directly responsive to said response indicating that said responder node is unavailable to respond to said transaction, for retrying said transaction. In this manner, a retry mechanism can be implemented on a bus which does not directly support a retry signal.

Abstract: The present invention relates to an interval width update process in arithmetic coding, characterized in thata set of values ={A[0],A[1], . . . ,A[r-1]}, is selected and the interval width is maintained as an index Wi in said set,a single table lookup simultaneously updates the interval width and supplies the augend and shift by performing the following operation:(Wi+1, Xi, Ri)=.function."(Si, Wi)in which the function .function." is implemented by a single table lookup, in which p(Si) and P(Si) are determined from Si, A[Wi] is determined from Wi, p(Si).multidot.A[Wi] and Ri=P(Si).multidot.A[Wi] are computed, the shift Xi necessary for representing p(Si).multidot.A[Wi].multidot.2.sup.Xi in is determined. Wi+1 is determined in such a way that A[Wi+1] is the best representative of p(Si).multidot.A[Wi].multidot.2.sup.Xi, followed by return to Wi+1, Xi and Ri.

Abstract: An apparatus which provides a high data transfer rate to and from an asynchronous bus. The apparatus includes a synchronous logic network to provide a transaction connection between the asynchronous bus and the data transfer device during an initial phase of the transaction when many determinations are required and an asynchronous logic network to provide data transfer between the asynchronous bus and the data transfer device during a subsequent phase of the transaction when very few determinations are required.

Abstract: A pipelined, microcoded CPU employs conditional branching in microcode execution Data path conditions produced by one microinstruction are used in the selection of a following microinstruction. In high-performance systems, multiple cycle microbranch latency requires that the generation of microbranch conditions be pipelined. Usually a microbranch condition is used exactly once, at the earliest possible time, when dynamic microbranch conditions are only valid a fixed number of microinstructions later in the pipeline. Flexibility of the microcode algorithm is increased by selectively inhibiting the update of the dynamic conditions to delay the use of the condition by one or more cycles, under microcode control, thereby implementing dynamic microbranches, while allowing use of previous dynamic microbranch state.

Abstract: A fault tolerant computer system is described in which a direct memory access controller examines the check bit data on every data element that is accessed by the system. The address of any data element that is found to have an error in the check bit data is stored by the direct memory access controller, the check bit data is used by the direct memroy access controller to correct the error, and the corrected data element is rewritten to the original storage address. By the use of this arrangement, the central processing unit or units of the computer system are free to perform other tasks, thus improving system throughput, and preventing the accumulation of data element errors in the memory.

Abstract: A page mode/nibble mode dynamic random access memory (DRAM) comprising row and column decoders, the column decoder further comprising a column address buffer and a column address buffer counter. The page mode/nibble mode DRAM also comprises a buffer controller means adapted to receive a write enable signal and to determine whether the DRAM should be placed in a page mode or a nibble mode to facilitate the particular memory access requested by a memory controller. An asserted write enable signal, may indicate, for example, a write operation, thereby calling for the page mode/nibble mode DRAM to move into a page mode to effectuate the write operation. The page mode/nibble mode DRAM also utilizes the write enable signal in the conventional manner, to indicate the initiation of a particular type of memory access, namely a write operation or a read operation.

Abstract: A thermosiphon provides cooling for a high powered die. The thermosiphon includes a fuse for accommodating temperature fault conditions. The thermosiphon utilizes a water and alcohol mixture for improved boiling characteristics. Contaminants at the joint betweeen the thermosiphon and the package housing are reduced by the use of a shrink ring seal. Thermal interfaces between the die and the thermosiphon are eliminated by directly coupling the die to the thermosiphon.

Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by said set of instructions, to reorder the issuance of said set of instructions from said instruction processor. The mapped register operand fields are associated with the corresponding instructions of said reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: A work flow description database represents long running work flows as a set of work units, called steps, with information flows therebetween. The description database defines each step's input and output signals, input condition criteria for creating an instance of the step, an application program associated with the step, and criteria for selecting a resource to execute the step. A work flow controller controls the process of executing instances of each defined type of work flow. Execution of a long running work flow begins when a corresponding set of externally generated input event signals are received by the work flow controller. During execution of a work flow, each step of the work flow is instantiated only when a sufficient set of input signals is received to execute that step. At that point an instance of the required type of step is created and then executed by a selected resource.

Abstract: Multi-processor systems are often implemented using a common system bus as the communication mechanism between CPU, memory, and I/O adapters. It is also common to include features on each CPU module, such as cache memory, that enhance the performance of the execution of instructions in the CPU. Many architectures require that the hardware employ a mechanism by which the data in the individual CPU cache memories is kept consistent with data in main memory and with data in other cache memories. One such method involves each CPU monitoring transactions on the system bus, and taking appropriate action when a transaction appears on the bus which would render data in the CPU's cache incoherent. If the CPU uses queues to hold records of incoming transaction information until it can service them, the bus interface must guarantee that the queued items are processed by the cache in the correct order. If this is not done, certain types of shared data protocols fail to operate correctly.

Abstract: An output device is enabled to obtain character descriptions for use in raster scanning characters which belong to a common character font. Character descriptions are stored in an external device which is linked to the output device by a communication channel. Character codes are received at the output device which identify characters to be outputted. A raster image of the characters to be outputted is set up. In the course of setting up the raster image, information corresponding to the character codes is sent from the output device to the external device via the communication channel. In response to the character codes sent from the printer to the external device, corresponding character descriptions are sent from the external device to the output device via the communication channel.

Abstract: A method of forming cobalt silicide on source/drain regions and polysilicon gate areas of an MOS integrated circuit uses an improved technique to prevent unwanted oxidation of cobalt or growth of silicide on other areas of device. A thin titanium nitride (or titanium tungsten) film is deposited on top of a cobalt film following the steps of patterning the polysilicon gate, source/drain implant and sidewall oxide spacer deposition and etch. The titanium nitride film allows formation of defect-free cobalt silicide during an elevated-temperature anneal. Without the titanium nitride film, the cobalt is likely to oxidize and/or form cobalt silicide in unwanted regions of the device, which can cause device failure.

Abstract: A content addressable memory has a pair of single-bit memory cells together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state. Each of the memory cells has a pair of transistors. One of the transistors connects a common node to a respective one of a pair of address lines, and another of the transistors connects the common node to a potential of a predefined logic level. Each of the transistors has a gate receiving a logic level of the bit of information stored in a respective memory cell so that one of the transistors is conductive in response to the logic level of the bit of the information when the other of the transistors is not conductive in response to the logic level of the bit of information. Each of the memory cells also includes a transistor connected to the match line and having a gate connected to the common node.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.