Abstract: A method of remote debugging comprises a first computer system that communicates with a second computer using a network connection. The first computer system controls the remote debugging and comprises a first operating system. The second computer system comprises a second operating system and software being tested. User input, in the form of debug commands, is received using a remote debugger in the first computer system to control the remote debugging session. The remote debugger translates a debug command into messages that are sent from the first computer system to the second computer system. The messages correspond to tasks that the target computer system performs to complete the debug command. During debugging, the target computer system transitions between polling or stopped mode and interrupt-driven mode by transitioning both the target operating system and network hardware in the target computer system that interfaces with the network.

Abstract: A computer system includes a central processing unit which further includes an execution unit and two levels of data cache and an error checking and correcting unit. During error-free operation, external cache fill data is supplied directly to the execution unit while a copy of the data is checked by the error checking and correcting unit. In response to detection of an error by the error checking and correcting unit, the use of the fill data by the execution unit is aborted. Furthermore, the data path for fill data is dynamically reconfigured to force remaining pending fill data to pass through the error checking and correcting unit prior to reaching the execution unit or either of the caches. Once all pending fill data has been processed, the data path is reconfigured back to its error-free mode of operation such that fill data is transmitted directly to the execution unit while a copy of the data is checked by the error checking an correcting unit.

Abstract: A computer system executing virtual memory management and having a cache is operated in a manner to reduce cache misses by remapping pages of physical memory from which cache misses are detected. The method includes detecting cache misses, as by observing cache fill operations on the system bus, and then remapping the pages in the main memory which contain the addresses of the most frequent cache misses, so that memory references causing thrashing can then coexist in different pages of the cache. For a CPU executing a virtual memory operating system, a page of data or instructions can be moved to a different physical page frame but remain at the same virtual address, by simply updating the page-mapping tables to reflect the new physical location of the page, and copying the data from the old page frame to the new one.

Abstract: The present invention is directed to a method of managing a cache upon detection of an address TAG parity error, The cache includes a plurality of entries for storage of data, with each entry having a corresponding address TAG entry. The method includes the steps of performing a TAG parity check for each access to the cache, and upon detection of a parity error in an address TAG, disabling allocation of TAG entries for storage of new address TAGs. A signal indicating the TAG parity error is transmitted to an error correction mechanism.

Abstract: Power bus bars are provided for a semiconductor die. Power bus bars are thick electrical conductors that extend the length of the die in an electrically isolated array of stripes. The electrical stripes are divided into two or more interdigitated groups, each group connected to a power supply, or connected to a ground supply. This arrangement of alternate power and ground stripes minimizes inductance and resistance, and brings power and ground close to every transistor in the semiconductor die with minimized voltage variations.

Abstract: A pipelined floating point processor including an add pipe for performing floating point additions described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky bit" from the input operands, and a rounding adder which adds a pair of operands and rounds the result in a single pipeline stage operation. The rounding adder incorporates effects due to rounding in select logic for a series of carry select adders. The adder also aligns the datapath to permit economical storage and retrieval of floating point and interger operands for floating point or conversions operations. The floating point processor also includes in the adder pipeline a divider circuit include a quotient register having overflow quotient bit positions to detect the end of a division operation.

Abstract: Methods for handling exceptions caused by speculatively scheduled instructions or predicated instructions executed within a computer program are described. The method for speculatively scheduled instructions includes checking at a commit point of a speculatively scheduled instruction, a semaphore associated with the speculatively scheduled instruction and branching to an error handling routine if the semaphore is set. A set semaphore indicates that an exception occurred when the speculatively scheduled instruction was executed. For a predicated instruction the method includes checking a predicate of an eliminated branch and a semaphore associated with the speculative instruction at a commit point of the speculative instruction and branching to an error handling routine if the semaphore indicates that an exception occurred when said speculative instruction was executed, and the predicate is true, which indicates that said speculative instruction was properly executed.

Abstract: A synchronous computer system is described. The system is a multiprocessor system having a bus system clock and a processor clock for each processor. The system includes a synchronous computer system bus and a plurality of circuit modules coupled to the synchronous bus with at least two of the modules having at least one processor, with the processor modules having the at least one processor which runs asynchronously to each of the other processors while the processor modules are synchronous to the system bus. The system further includes clock generator means for providing a corresponding plurality of clock signals and a plurality of conductors coupled between said clock generating means and said plurality of modules.

Abstract: A method and system for compiling a source program using smart recompilation. The invention allows fragments to contain "invocation specific" information, which is generated during a code generation phase of compilation. A hint generator attempts to preserve values of the invocation specific information between successive invocations of the compiler.

Abstract: In response to a message requesting a method invocation from an application or user, a client application determines the proper method to be invoked by retrieving information from a class data base, comparing the retrieved information with user preferences, and selecting the proper method based upon the comparison. Server connection and start-up involves locating a platform capable of executing code associated with the selected method and, if necessary, executing a process to start an application associated with the selected method.

Abstract: A pipelined processor includes an instruction box including a register mapper, to map register operand fields of a set of instructions and an instruction scheduler, fed by the set of instructions, to reorder the issuance of the set of instructions from the instruction processor. The mapped register operand fields are associated with the corresponding instructions of the reordered set of instructions prior to issuance of the instructions. The processor further includes a branch prediction table which maps a stored pattern of past histories associated with a branch instruction to a more likely prediction direction of the branch instruction. The processor further includes a memory reference tagging store associated with the instruction scheduler so that the scheduler can reorder memory reference instructions without knowing the actual memory location addressed by the memory reference instruction.

Abstract: An ESD protection device is provided which includes a self referencing modulation circuit for controlling its operation. The modulation circuit includes a diode stack coupled to a resistor and further coupled to an inverter powered by the signal pad voltage in one embodiment, or an odd plurality of series connected inverters powered by the signal pad voltage in an alternate embodiment. The inverter chain is coupled to the ESD clamp. The modulation circuit requires no reference supply voltage to operate. The ESD protection circuit shunts currents associated with ESD events away from ICs as well as clamping I/O pad voltages to acceptable levels during an ESD event.

Abstract: A computer system comprising one or more processor modules. Each processor module comprising a central processing unit comprising a storage element disposed in the central processing unit dedicated for storing a semaphore address lock value and a semaphore lock flag value, a cache memory system for storing data and instruction values used by the central processing unit, a system bus interface for communicating with other processor modules over a system bus, a memory system implemented as a common system resource available to the processor modules for storing data and instructions, an IO system implemented as a common system resource available to the plurality of processor modules for each to communicate with data input devices and data output devices, and a system bus connecting the processor module to the memory system and to the IO system.

Abstract: A pattern recognition device tracks the angular movements made by a pointing device such as a mouse in generating a pattern of lines. A pattern code is generated if the angular movements match those of a pattern code in a lookup table. The pattern matching for the shape is done without regard to size, is insensitive to expected variations in hand-drawn strokes, requires minimal computer processing and data storage, and can distinguish between identical patterns that differ only in the order in which their constituent line segments were drawn.

Abstract: A digital computer system having a prototype list, an activation identifier, and a control portion. The prototype list having a plurality of entries each associated with a prototype object, at least some entries including an interaction list for specifying prototype objects and actions. The activation identifier identifies activation of an instance of an object; and the control portion is responsive to the identification, by the action identifier, of activation of an object for performing operations on objects as-identified by the interaction list of a prototype entry associated with the instance of the activated object.

Abstract: A process is provided for developing a new computer system based on a new (Y) architecture. A Y computer prototype is developed with a design in accordance with the Y architecture.A multi-code processing system is developed for use on an existing X computer system designed in accordance with an X architecture and having an operative X operating system and operative X support routines. The processing system includes a Y simulator component, a debugger component, and an environment manager component. A Y code module is developed for each of a plurality of predetermined Y program modules during the Y prototype development.The multi-code processing system and at least one of the Y code modules are loaded into the X computer system during the Y prototype development. A related X code module may also be processed for loading into the X computer at the same time.

Abstract: A compiler framework uses a generic "shell" and a generic back end (where the code generator is target-specific). The generic back end provides the functions of optimization, register and memory allocation, and code generation. The code generation function of the back end may be targeted for any of a number of computer architectures. A front end is tailored for each different source language, such as Cobol, Fortran, Pascal, C, C++, etc. The front end scans and parses the source code modules, and generates from them an intermediate language representation of the source code programs expressed in the source code. The intermediate language represents any of the source code languages in a universal manner, so the interface between the front end and back end is of a standard format, and need not be rewritten for each language-specific front end. A feature is a method for doing code generation using code templates in a multipass manner.

Abstract: Disclosed is a semiconductor package and method in which a semiconductor chip is mounted within the opening of a lead frame by bonding wires extending between the active front side of the chip and bonding pads of the lead frame, and the lead frame/chip assembly is encased. within a plastic molded body, with the inactive back side of the chip exposed and facing outside the package.

Abstract: This disclosure relates to an image processing system which relies upon quantization and dithering techniques to enable an output device, which has a given number of output levels, to accurately reproduce a image which is generated by an input device, which has a greater or equal number of input levels. Generally, neither the number of input nor output levels need to be a power of two. The present invention is implemented in a number of different embodiments. These embodiments generally rely upon an image processor which, depending on the particular implementation, includes memory devices and an adder, a comparator, or a bit shifter. Additional embodiments use an image adjustment system or an image modification system to refine the raw input levels of the input device, in order to create an improved output image. Also, the particular embodiments of the image processors can be used in connection with imaging systems having bi-tonal, monochromatic, or color input and output devices.

Abstract: A fan heatsink assembly is provided to afford cooling for electronic components mounted on a circuit board. The assembly includes a blower mounted on top of a specially shaped heatsink, the heatsink having a truncated hyperbolic shaped central member, with fins radially emanating from the center. The blower draws air in through the area between the fins, up the curved central portion and into the blower assembly where it is then exited out the sides of the fan. The fins may be smooth or textured, straight or curved. The fan heatsink assembly is attached to the device to be cooled. Heat is transferred from the electronic component, into the heat dissipating member where the fan causes air to be drawn up between the fins and along the curved center portion, removing heat from the heat dissipating member and the electronic component.