Abstract: A method and system for compiling a source program using smart recompilation. The invention allows fragments to contain "invocation specific" information, which is generated during a code generation phase of compilation. A hint generator attempts to preserve values of the invocation specific information between successive invocations of the compiler.

Abstract: A fixture (10) for bonding multiple components together includes a bottom plate (20), a middle plate (22) and a top plate (24). The plates (20), (22) and (24) are aligned by dowels (26) and clamps (30). Bottom plate (20) has a rectangular pocket (32) for holding heat sink (14) and alignment pins (34) for locating plastic pin grid array (PPGA) package (12) over the heat sink (14). An annular projection (40 ) covered with a conformal pad (42) extends from bottom surface (44) of the middle plate (22). Dowel (50) extends through openings (46) and (36) in the top and middle plates (24) and (22) to apply pressure to chip (16). A first spring (56) is mounted on the dowel (50) and compressed between the top plate (24) and a snap ring (58) to provide pressure from the dowel (50 ) on the chip (16). A second, larger diameter spring (60) is compressed between the middle plate (22) and the top plate (24) to provide pressure from the middle plate (22) on the PPGA (12).

Abstract: A method of testing an integrated circuit having a plurality of pins includes the steps of providing a functional test set having an ordered group of test strings wherein each element of the test string is related to one of the pins of said integrated circuit. The group of test strings is searched to locate a sequence of test strings having a undesirable pattern. The undesirable pattern can be a pattern in which none of the elements associated with the test string changes or a pattern in which a reference element and at least one other element of the test string changes. When a sequence of test strings having the undesirable pattern is located, the group of test strings is processed to correct the undesirable pattern. When all the vector sequences having an undesirable patterns are corrected, the group of test vectors is applied to the input pins of the integrated circuit.

Abstract: A circuit board is ejected from an electrical chassis by inserting a pair of implements into corresponding pairs of apertures disposed on opposing side members of the electrical chassis. The end portions of the implements are engaged in a first pair of notches, each one being disposed on each of a pair of opposing edges of the circuit board provided within the electrical chassis, and a force is exerted on each of the first notches disposed on each of the pair of opposing edges of the circuit board with the pair of implements, to disengage the circuit board from a connector located at one end of the electrical chassis.

Abstract: A load/store pipeline in a computer processor for loading data to registers and storing data from the registers has a cache memory within the pipeline for storing data. The pipeline includes buffers which support multiple outstanding read request misses. Data from out of the pipeline is obtained independently of the operation of the pipeline, this data corresponding to the request misses. The cache memory can then be filled with the requested for data. The provision of a cache memory within the pipeline, and the buffers for supporting the cache memory, speed up loading operations for the computer processor.

Abstract: A computer system provides transactional memory operations, in which a selected data item in a shared memory is referenced by a CPU in local storage (such as a write-back cache). The CPU performs some operation to alter or use the data item while it is in local memory, and meanwhile monitors the bus to the shared memory to see if another processor references the selected location (as by a snoop mechanism); if so, a status bit is toggled to indicate that the transaction must be scrubbed. When the operation has been completed by the CPU, it attempts to "commit" the transaction, and this includes checking the status bit; if the bit has been toggled, the transaction aborts, the data item is invalidated in local memory, and the selected location in shared memory is not affected. If the status bit has not been toggled, the transaction is committed and the altered data item becomes visible to the other processors, and may be written back to the shared memory.

Abstract: A radial clock distribution system that converts a standard bus clock signal into two pairs of inverted and non-inverted clocking signals. The two pairs of clocking signals have a lower frequency, have a different phase, and are shifted one clock period apart. The clocking signals are transferred over a first set of signal lines of equal length and impedance to computing systems components that are connected to a synchronous bus. Each component includes at least one clock repeater chip to convert the clocking signals (e.g., change these signals to a 5 volt CMOS level) to a different format. The converted clocking signals are then transferred over a second set of signal lines of equal length and impedance to the gate arrays. The gate arrays includes direct drive circuitry that receives the converted clocking signals and transmits these signals to internal driver circuitry. These signals are transferred over low skew lines.

Abstract: A switch circuit is disclosed which both sets the voltage at an output terminal and signals that the voltage has been set. The switch circuit may be implemented with a single-pole single-throw switch. A voltage drop device, connected in parallel with the switch, is used to generate the output voltage levels. The switch circuit is also suitable for enabling and disabling the heartbeat signal generated by a local area network transceiver and for signaling whether the heartbeat signal has been enabled by lighting a light-emitting diode.

Abstract: A monitor for monitoring the occurrence of events on the bus (15) of a multiprocessor computer system. The bus event monitor (BEM) includes a dedicated BEM processor (23) and an event counter subsystem (25). During each bus cycle, the BEM (21) captures and interprets the packet of data being transmitted on the bus (15). If the packet represents an event designated by the user to be of interest, a counter associated with the type of packet that was captured and interpreted is incremented by one. More specifically, a field programmable gate array (FPGA), configured by the user, defines the type of events to be counted. When an event to be accounted occurs, the FPGA (33) produces a counter address that is based on the nature of the event, and causes an enable pulse to be generated. The address is applied to the active one of two event counter banks (39a, 39b) via an input crossbar switch (37a). The enable pulse enables the addressed event counter to be incremented by one.

Abstract: A process for filling an isolation trench with a dielectric is described. The deposition pressure of a gas from which a silicon dioxide dielectric is deposited in a trench is changed on a real-time basis during such deposition. Such pressure gradually increases from about 20 mTORR to 900 mTORR. The result is that particle generation during the initial stages of the deposition is maintained at a low rate, while the high pressure needed to provide deposition in a trench as it is filled is provided.

Abstract: A digital computer system includes a scalar CPU, a vector processor, and a shared cache memory. The scalar CPU has an execution unit, a memory management unit, and a cache controller unit. The execution unit generates load/store memory addresses for vector load/store instructions. The load/store addresses are translated by the memory management unit, and stored in a write buffer that is also used for buffering scalar write addresses and write data. The cache controller coordinates-loads and stores between the vector processor and the shared cache with scalar reads and writes to the cache. Preferably the cache controller permits scalar reads to precede scalar writes and vector load/stores by checking for conflicts with scalar writes and vector load/stores in the write queue, and also permits vector load/stores to precede vector operates by checking for conflicts with vector operate information stored in a vector register scoreboard.

Abstract: A novel switch architecture maintains the sequence of packet cells, received at one port of a multicast port group, during subsequent transfer of the cells to the remaining ports of the group. The novel architecture includes a 2-stage buffering arrangement whereby the first stage comprises a plurality of local buffers, each associated with a port of the switch, and the second stage comprises a single, global buffer. Each local buffer services its associated port of the multicast port group by temporarily storing incoming packet cells until a complete packet is received at that port, at which time the packet cells may be passed to the global buffer as outgoing cells. The global buffer services the remaining ports of the multicast port group by forwarding copies of the outgoing cells, in sequence, to those ports.

Abstract: The invention relates to a switching power supply having a protection device to shut down the supply of the output voltage in the presence of a fault condition such as an overload. The invention identifies potential fault conditions when the voltage control feedback loop is out of regulation and screens out false fault conditions during periods when the duty cycle of the control signal is below a specified duty cycle limit. The invention further shuts down the supply of the output voltage when the bulk line voltage provided to the power supply is below a specified limit.

Abstract: A method and apparatus for optimizing the performance of a multibus data processing system is provided. An I/O controller is coupled to the I/O bus and includes MORE bit setting means for initiating a MORE stream transaction on the I/O bus and for thereafter terminating the MORE stream transaction. An adapter coupling the I/O bus to the system bus, is configured to receive the MORE stream transaction and transfer it to main memory. The adapter includes MORE bit decoding means for identifying the beginning and the end of the MORE stream transaction, and for identifying whether the MORE stream transaction is a READ or WRITE transaction. The adapter also includes a first buffer for receiving data from the I/O bus and transferring the data to the memory in accordance with the memory's full block transfer size, and a second buffer for receiving a full block of data and transferring that data in accordance with the I/O bus transaction limitations.

Abstract: A memory management and arbitration technique that reduces system bus contention by eliminating memory bank conflicts employs a restrictive, distributive memory-arbitration scheme, and an improved address decoder for decoding addresses of software reconfigurable memory. In the memory-arbitration scheme, each commander node desiring access to a particular memory bank first determines whether that memory bank is "available" before initiating access to that memory bank, with the determination being made before requesting control of the system bus. A memory bank is "available" if it was not accessed during a predetermined number (e.g., two) of the immediately previously-occurring arbitrations for the system bus. The address decoder includes a mapping register that stores information concerning the addresses assigned to, and the structure of, the memory module. The address decoder also has an address/range decoder section, an interleaved decoder section, and a bank decoder section.

Abstract: A parallel air flow system which automatically maintains proper coolant flow regardless of the number of circuit boards installed in an enclosure. The enclosure is constructed such that air flow path through any one slot does not affect the air flow through any other slot. Proper air flow through the entire system is maintained by an air flow sensor disposed in an air flow path having a known air flow resistance. This sensor controls the speed of an air-mover in order to maintain a constant predetermined air flow through the known resistance, in such a way that a constant static air pressure is maintained at each slot. Baffle modules are preferably inserted into the enclosure to prevent air flow into any empty slots, to reduce the total air volume necessary to achieve the predetermined static pressure, thereby reducing the audible noise generated by the air-mover.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes.

Abstract: A phase delay compensator apparatus is provided which compensates for the phase error caused by propagation delay differences between clock and data paths within a computer system. A look-up table circuit is used to dynamically translate a change in frequency of the computer system clock or a change in the length of cable connecting the computer's sub-assemblies to a binary bit pattern defining the requisite phase-shift between distributed clock and data signals. A generator circuit produces phases of the phase-shifted clock signals, while ensuring the integrity of the loaded binary bit pattern. A gated signal is created for enabling the generator circuit.

Abstract: An apparatus which allows for software sharing between multiple controllers includes a computer bus and a plurality of processors each having input and output ports coupled to the bus. Each processor also has at least one internal storage register. The apparatus further includes means, which are responsive to a signal indicating which one of the plurality of processors is controlling the computer bus and to a portion of address data on the bus, for issuing a control signal to one of the plurality of processors to permit that one processor access to at least one of its internal storage register when that processor issues a bus access request having an address which is within the range of addresses of all the processors.

Abstract: An X window display server provides a virtual window manager client that, from the viewpoint of client programs connected to the server, is indistinguishable from a real window manager client. The emulated window manager is implemented as an internal server client.