Abstract: A semiconductor memory device according to the invention includes a main memory comprising a number of memory sub-arrays, each coupled to an address and a data bus, for providing or receiving data to an intermediate interface unit. The intermediate interface unit provides data to and receives data from an output bus. Also included in the semiconductor memory device is redundancy circuit including a redundant memory coupled to the output bus for storing a subset of data from one of the sub-arrays in the event that the sub-array is defective. The redundancy circuit additionally includes address fuses for storing the sub-array addresses of the subset of data to be stored in the redundant storage, and compare circuitry coupled to the address bus for comparing the address bus to the stored array addresses to determine if there is a match.

Abstract: A new method for planarization of shallow trenches is presented. Shallow trenches are patterned into a semiconductor substrate that has been coated with a layer of silicon nitride. A conformal coating of oxide is deposited onto the wafer to fill the trenches. A thin layer of etch-stop silicon and a second layer of oxide are then deposited. The second layer of oxide is patterned with a filler mask using conventional photolithographic techniques and etched to the silicon etch-stop layer, leaving blocks of oxide in the depressions above the trenches and oxide spacers along the sidewalls. Chemical mechanical polishing is then used to polish the oxide back to the silicon nitride. The process offers excellent global planarity, minimal variation in silicon nitride thickness across active areas of varying size and density, and relative insensitivity to chip design.

Abstract: This invention relates to an image processing system which relies upon quantization and dithering techniques to enable an output device, which has a given number of output levels, to accurately reproduce a image which is generated by an input device, which has a greater or equal number of input levels. Generally, neither the number of input nor output levels need to be a power of two. The present invention is implemented in a number of different embodiments. These embodiments generally rely upon an image processor which, depending on the particular implementation, includes memory devices and an adder, a comparator, or a bit shifter. Additional embodiments use an image adjustment system to refine the raw input levels of the input device, in order to create an improved output image. Also, the particular embodiments of the image processors can be used in connection with imaging systems having bi-tonal, monochromatic, or color input and output devices.

Abstract: This disclosure relates to a process for laser soldering surface mount components on a printed circuit board using the continuous wave laser scanning technique. The process involves factoring together the scan rate, the beam diameter, and the laser power level, in order to determine what these specific process variables should be. In addition, the process also involves taking account of the depth of a metallic layer, such as a reference plane, inside the printed circuit board to determine its effect on other process variables. On the other hand, if the board does not have a metallic layer, the process takes account of the thickness of the board being processed. Preferred ranges for process variables are identified, as well as optimization techniques which further refine the process variables to achieve production efficiency or bonding pull strength.

Abstract: Disclosed is a method of planarizing the surface of a silicon wafer in integrated circuit manufacture where shallow trench isolation techniques are employed. The etched trenches are first coated with a silicon nitride protective liner before the trenches and active area mesas are conformally coated with a layer of silicon oxide. The conformal oxide then is steam annealed to densify the conformal oxide, and then the surface of the silicon wafer is etched and polished back down to the tops of the active area mesas, to form a substantially planar surface.

Abstract: In general, in one aspect, the invention features a fastener having two mating pieces. One of the mating has a rigid surface of thickness q, and a hole in the surface, the hole including a slot defined by two generally parallel edges separated by a distance r. The other mating piece has a base and a pair of wings held above the base to define two generally parallel channels spaced to accommodate the two parallel edges of the slot, the channels having a thickness greater than q, the span of the wings being greater than r.

Abstract: A fault-tolerant computer system has primary and backup computers. Primary and backup virtual machines running on the computers are controlled by corresponding virtual machine monitors. The virtual machines execute only user-mode instructions, while all kernel-mode instructions are trapped and handled by the virtual machine monitors. Each computer has a recovery register that generates a hardware interrupt each time that a specified number of instructions, called an epoch, are executed. Prior to failure of the primary computer, the backup computer's virtual machine monitor converts all I/O instructions into no-ops and the primary computer sends copies of all I/O interrupts to the backup computer.

Abstract: A data dependency scoreboard for a pipelined digital computer includes a source counter and a destination counter for each general purpose register (GPR). The source counter for each GPR is incremented each time that a specifier is decoded that specifies the use of the source counter's GPR as a source operand. The source counter is decremented each time that an execution unit reads a source operand from the source counter's GPR. The destination counter is incremented each time that a specifier is decoded that specifies the use of the counter's GPR as a destination operand. The destination counter is decremented each time that the execution unit writes to the destination counter's GPR. A data dependency conflict causing a complex specifier unit to stall occurs when operand processing requires a write to a GPR that has a source counter value greater than zero, and when operand processing requires a read of a GPR that has a destination counter value greater than zero.

Abstract: An array processing system has a plurality of processing elements, each of which includes a processor and an associated memory module, and a router network over which each processing element can transfer messages to other random processing elements. The system further includes a shift register which can shift data either toward a shift-in terminal, or toward a shift-out terminal, either one bit at a time or four bits at a time, thus improving processing system speed for floating point arithmetic operations.

Abstract: A system and method for controlling execution of nested loops in parallel in a computer including multiple processors, and a compiler for generating code therefor. The code enables the computer to operate in the following manner. Each processor processes an iteration of an outer loop in a set of nested loops. If the outer loop contains more iterations than processors in the system, the processors are initially assigned early iterations, and the later iterations are assigned to the processors as they finish their earlier iterations, until the processors have processed all of the iterations. Each processor, during processing of an outer loop iteration runs the iterations comprising the inner loop serially. In order to enforce dependencies between the loops, each processor reports its progress in its iterations of the inner loop to the processor executing the succeeding outer loop iteration.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: In a pipelined digital computer, an instruction decoder decodes register specifiers from multiple instructions, and stores them in a source queue and a destination queue. An execution unit successively obtains source specifiers of an instruction from the source queue, initiates an operation upon the source specifiers, reads a destination specifier from the destination queue, and retires the result at the specified destination. Read-after-write conflicts may occur because the execution unit may overlap execution of a plurality of instructions. Just prior to beginning execution of a current instruction, the destination queue is checked for conflict between the source specifiers of the current instruction and the destination specifiers of previously issued but not yet retired instructions. When an instruction is issued for execution, its destination specifiers in the destination queue are marked to indicate that they are associated with an executed but not yet retired instruction.

Abstract: Transformers (T1, T2), switches (M1) and (M2), rectifiers (DR1, DR2, DR3, DR4) and low-pass filter (LF, CF) form a basic power train circuit (12). Auxiliary switches (A1, A2), diodes (DS1, DS2) and capacitors (CS1, CS2) form active clamp circuit (10). The capacitances for (CS1, CS2) are chosen large enough such that the voltages (vCS1, vCS2) across the capacitors are essentially constant during several switching cycles. Switches (M1) and (A1) are driven by the signal (V.sub.G1), while switches (M2) and (A2) are driven by (V.sub.G2). When (M1) is turned OFF, the energies stored in the magnetizing and leakage inductances in (T1) will resonate with the output capacitance of (M1) first. When the voltage (V.sub.M1) across (M1) exceeds the voltage (V.sub.CS1) across (CS1), (DS1) conducts and (V.sub.M1) is clamped at (V.sub. CS1), which has a steady-state value of slightly less than two times the input voltage (E). During this interval, the capacitor (CS1) is charged by the leakage inductor current (i.sub.LK1).

Abstract: A filtering attachment is provided for the reduction of common-mode noise in systems. The filtering attachment includes a connector, a ferrite fitted around the connector and a conductive bracket which serves to secure the ferrite around the connector as well as comprising a shunting capacitance for increased filtering.

Abstract: An I/O bus interface cell includes a driver circuit having an input terminal fed by a logic signal and an output terminal to produce in response thereto a drive signal having selectable rise and fall time characteristics in accordance with a reference voltage provided to the driver. The I/O cell also includes a receiver circuit having an input terminal coupled to said output terminal of said driver with the receiver disposed to latch an unresolved, unamplified received signal prior to resolving the state of the signal. The I/O cell further includes a termination circuit having a terminal connected to the output of said driver, and having a selectable impedance characteristic at said terminal, with said selectable impedance being in accordance with a reference voltage provided to an input of said termination circuit. Preferably, the I/O cell a the driver, receiver and termination circuits are fabricated on a common semiconductor substrate.

Abstract: A cash pocket for an automatic teller machine (ATM) comprises a housing having a rear wall with a slot for receiving banknotes from the dispensing mechanism of the ATM into the housing, and a base upon which the dispensed banknotes come to lie upon being dispensed into the housing. The housing also has a front panel having an opening for the withdrawal of notes by a user of the ATM, the opening having a door which pivots about an axis substantially parallel to the longitudinal axis of the slot from a first position in which the front opening is closed to a second position in which the front opening is open for the withdrawal of dispensed banknotes. The door includes a pair of flanges which block access to the slot from the front opening when the door is open or partially open.

Abstract: A high-performance central processing unit (CPU) of the reduced instruction set (RISC) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. The processor can employ a variable memory page size, so that the entries in a translation buffer for implementing virtual addressing can be optimally used. A granularity hint is added to the page table entry to define the page size for this entry.

Abstract: An integrated circuit chip has both digital and analog circuit functions, with one or more islands for isolating the analog functions from noise caused by the digital functions. An island is defined by a surrounding heavily-doped region in the face of the chip. The voltage supplies for an analog island are isolated from the digital supply voltage for high frequencies by using resistive decoupling in series along with capacitive coupling to ground. Similarly, series resistive decoupling and capacitive coupling to ground are employed for the analog input signal lines going to the island. Analog signals generated within the island are coupled to the area outside the island on the chip face by either converting to digital in an A-to-D converter, or by a differential arrangement which accounts for differences that may exist between digital and analog supply voltages.

Abstract: A pipelined processor has an instruction unit for decoding instructions and pre-processing operands prior to instruction execution, and an execution unit for executing the decoded instructions. The pre-processing of operands includes changes to general purpose registers, and the changes are recorded in an RLOG queue having read and write pointers. Instruction context for the RLOG queue entries is maintained in a separate RLOG base queue. When decoding begins for a new instruction, the RLOG base queue is loaded with the RLOG write pointer to the first RLOG queue entry that would record a register change for that next instruction. Each time an operand is processed that changes a general purpose register, the value of the change is recorded in the entry pointed to by the RLOG queue write pointer, and the RLOG queue write pointer is advanced.

Abstract: A system for evaluating the performance of a computer system having a processor that passes through a plurality of processor states during operation and an associated system memory includes an operating unit for receiving a request to monitor specific process states from a user. Firmware causes the processor to enter the desired processor state requested by the user. The hardware identifies the occurrence of the desired processor state. Information relating to the occurrence of the desired process state is accumulated the memory. The accumulated information is read from memory and a report is provided to the user.