Abstract: Stacked semiconductor chips. One embodiment provides a device having a first body. A first power semiconductor chip and first external contact elements is provides. A second body includes a second semiconductor chip and second external contact elements. The second body is placed over the first body. The first external contact elements and the second external contact elements define a first plane.

Abstract: A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.

Abstract: A field plate trench transistor having a semiconductor body. In one embodiment the semiconductor has a trench structure and an electrode structure embedded in the trench structure. The electrode structure being electrically insulated from the semiconductor body by an insulation structure and having a gate electrode structure and a field electrode structure. The field plate trench transistor has a voltage divider configured such that the field electrode structure is set to a potential lying between source and drain potentials.

Abstract: A high pressure fluid system includes a sealing mechanism, which provides a fluid seal for a cylindrical bore via pressing contact between a first convex, curved surface at an end of the cylindrical bore and a second convex, curved surface at a containment element that is coupled relative to the end of the cylindrical bore.

Abstract: An integrated circuit device includes a semiconductor chip and a control chip at different supply potentials. A lead chip island includes an electrically conductive partial region and an insulation layer. The semiconductor chip is arranged on the electrically conductive partial region of the lead chip island and the control chip is cohesively fixed on the insulation layer.

Abstract: A semiconductor device and method is disclosed. One embodiment provides an active region in a semiconductor substrate, including a first terminal region and a second terminal region.

Abstract: A semiconductor device and method is disclosed. In one embodiment, the method includes placing a first semiconductor over an electrically conductive carrier. The first semiconductor is covered with a molding compound. A through hole is formed in the molding compound. A first material is deposited in the through hole.

Abstract: A method of manufacturing a semiconductor device includes attaching a first semiconductor substrate to a support substrate, and thinning the first semiconductor substrate to form a thinned semiconductor layer. The method additionally includes integrating a functional element with the thinned semiconductor layer, and forming at least one through-connect through the thinned semiconductor layer.

Abstract: A power semiconductor module assembly is disclosed including a power semiconductor module comprising a load terminal electrically conductively joined to a contact conductor. Part of the heat materializing during operation of the power semiconductor module in the load terminal is dissipated by using a heat dissipating element.

Abstract: A semiconductor device and method for manufacturing. One embodiment provides a semiconductor device including an active cell region and a gate pad region. A conductive gate layer is arranged in the active cell region and a conductive resistor layer is arranged in the gate pad region. The resistor layer includes a resistor region which includes a grid-like pattern of openings formed in the resistor layer. A gate pad metallization is arranged at least partially above the resistor layer and in electrical contact with the resistor layer. An electrical connection is formed between the gate layer and the gate pad metallization, wherein the electrical connection includes the resistor region.

Abstract: A module including a carrier and a semiconductor chip applied to the carrier. An external contact element is provided having a first portion and a second portion extending perpendicular to the first portion, wherein a thickness of the second portion is smaller than a thickness of the carrier.

Abstract: A sexually transmitted infection (STI) sampling device includes an elongated shaft that defines a first end separated from a second end, and an absorbent sampler coupled to one of the first and second ends. The absorbent sampler includes an absorbent core disposed on a longitudinal axis of the elongated shaft, and a plurality of fibers extending from the absorbent core. The plurality of fibers is configured to exfoliate and capture cells from a tissue surface of a patient, and the absorbent core is configured to absorb exfoliated cells not captured by the fibers.

Abstract: A system including magnetic sensing elements and a circuit. The magnetic sensing elements are configured to sense a magnetic field that is generated via a current and to provide signals that correspond to the magnetic field. The circuit is configured to determine calibration values based on the signals and measure the current based on the signals.

Abstract: A semiconductor component having a semiconductor body having a first and a second side, an edge and an edge region adjacent to the edge in a lateral direction is described.

Abstract: A silicon-on-insulator device having multiple crystal orientations is disclosed. In one embodiment, the silicon-on-insulator device includes a substrate layer, an insulating layer disposed on the substrate layer, a first silicon layer, and a strained silicon layer. The first silicon layer has a first crystal orientation and is disposed on a portion of the insulating layer, and the strained silicon layer is disposed on another portion of the insulating layer and has a crystal orientation different from the first crystal orientation.

Abstract: A semiconductor power switch and method is disclosed. In one Embodiment, the semiconductor power switch has a source contact, a drain contact, a semiconductor structure which is provided between the source contact and the drain contact, and a gate which can be used to control a current flow through the semiconductor structure between the source contact and the drain contact. The semiconductor structure has a plurality of nanowires which are connected in parallel and are arranged in such a manner that each nanowire forms an electrical connection between the source contact and the drain contact.

Abstract: A device with contact elements. One embodiment provides an electrical device including a structure defining a main face. The structure includes an array of cavities and an array of overhang regions, each overhang region defining an opening to one of the cavities. The electrical device further includes an array of contact elements, each contact element only partially filling one of the cavities and protruding from the structure over the main face.

Abstract: An electronic device includes at least one semiconductor chip, each semiconductor chip defining a first main face and a second main face opposite to the first main face. A first metal layer is coupled to the first main face of the at least one semiconductor chip and a second metal layer is coupled to the second main face of the at least one semiconductor chip. A third metal layer overlies the first metal layer and a fourth metal layer overlies the second metal layer. A first through-connection extends from the third metal layer to the fourth metal layer, the first through-connection being electrically connected with the first metal layer and electrically disconnected from the second metal layer. A second through-connection extends from the third metal layer to the fourth metal layer, the second through-connection being electrically connected with the second metal layer and electrically disconnected from the first metal layer.

Abstract: A method of manufacturing a semiconductor structure. One embodiment produces a substrate having at least two semiconductor chips embedded in a molded body. A layer is applied over at least one main surface of the substrate by using a jet printing process.

Abstract: A method removes moisture from a wall assembly including a supporting wall, an interior finishing layer attached to an interior side of the supporting wall, and an exterior layer disposed opposite the interior finishing layer. The supporting wall supports the interior finishing layer and exterior layer. The method includes sealing, with a moisture seal located between a base of the wall assembly and the supporting wall erected on the base, and providing a water separation plane disposed within the supporting wall so that the water separation plane is located between the interior finishing layer and the exterior layer. The water separation plane provides a substantial barrier to moisture vapor and bulk water. The method includes transporting moisture along an interior side and an opposing exterior side of the water separation plane to a moisture collection area outside of the wall assembly, and removing the moisture from the moisture collection area.