Patents Represented by Attorney DLA Piper US LLP
  • Patent number: 7405435
    Abstract: A semiconductor device includes a thyristor, trigger circuit and surge detection/leakage reduction circuit. The anode of the thyristor is connected to a first terminal and the cathode thereof is connected to a second terminal. The trigger circuit is configured to fire the thyristor when surge voltage is applied to the first terminal. The surge detection/leakage reduction circuit is provided between the gate of the thyristor and the second terminal and configured to interrupt current flowing from the trigger circuit to the second terminal in the normal operation mode and set trigger voltage which is used to fire the thyristor in cooperation with the trigger circuit at the surge voltage application time.
    Type: Grant
    Filed: October 4, 2004
    Date of Patent: July 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Koichi Sato
  • Patent number: 7406368
    Abstract: A security mechanism identifies users, so as to restrict access and operation to authorized users, such as to persons authorized to access and fly a particular aircraft. The security mechanism comprises one or more security devices to identify the user attempting to gain access or operate the controller; and one or more monitoring devices to determine whether or not the user identified is authorized to have access or operate the controller. Methods of safely operating aircraft are also described. The methods include protocols for limiting access to the aircraft and assuming remote control of the aircraft if a possibly hostile situation is detected.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: July 29, 2008
    Inventor: Michael Arnouse
  • Patent number: 7405988
    Abstract: Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transistor. For an NMOS sensing transistor, a triple well is used with the variable bulk voltage. Differential sense amplifiers with various offset compensation are included. Intentional offset creation for useful purpose is also included.
    Type: Grant
    Filed: September 26, 2005
    Date of Patent: July 29, 2008
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Hieu Van Tran, Hung Quoc Nguyen
  • Patent number: 7404957
    Abstract: This invention relates to modified IL-4 mutein receptor antagonists comprising an IL-4 mutein receptor antagonist coupled to polyethylene glycol. Related formulations and dosages and methods of administration thereof for therapeutic purposes are also provided. These modified IL-4 mutein receptor antagonists, compositions and methods provide a treatment option for those individuals afflicted with a respiratory disorder such as asthma by inhibiting IL-4 and IL-13-mediated airway hyperresponsiveness and eosinophilia. More particularly, these antagonists have an increased duration of effect versus unmodified IL-4RA by virtue of a greater plasma half-life.
    Type: Grant
    Filed: April 8, 2004
    Date of Patent: July 29, 2008
    Assignee: Aerovance, Inc.
    Inventors: Clark Pan, Steve Roczniak, Jeffrey Michael Greve, Stephanie L. Yung, Malinda Longphre, Teresa Mo-fun Wong, Adrian Tomkinson
  • Patent number: 7405920
    Abstract: A flat type capacitor-use polypropylene film having a Ad(thickness determined by micrometer method—thickness determined by weighing method) of 0.05-0.2 ?m and a lengthwise shrinkage dimensional change rate of 3% or less, or a flat type capacitor-use polypropylene film having a ?d of 0.1-0.3 ?m and a lengthwise F5 value of 50 MPa or more, and a flat type capacitor using it. A film excellent in handling ability in a capacitor element winding process is obtained, and a small, a large-capacity flat type capacitor excellent in withstand voltage characteristics such as self-recovering property, and used suitably under a high rated voltage, is obtained.
    Type: Grant
    Filed: March 16, 2004
    Date of Patent: July 29, 2008
    Assignee: Toray Industries, Inc.
    Inventors: Kimitake Uematsu, Isamu Moriguchi, Masahito Iwashita, Akira Oda
  • Patent number: 7406645
    Abstract: A test pattern generating apparatus includes an extractor configured to extract a plurality of layout parameters (elements) of a circuit under test based on gate net information and layout information of the circuit, and to link the layout parameters (elements) with corresponding fault models respectively. A weight calculator is configured to calculate a weight for each fault model linked with the layout parameters (elements) for both a plurality of undetected faults of the fault model and a plurality of faults detected by a plurality of test patterns, based on process failure (defect) information and layout parameter (element) information. An automatic test pattern generator is configured to generate the test patterns in accordance with the weight of each fault model linked with the layout parameters (elements).
    Type: Grant
    Filed: June 20, 2005
    Date of Patent: July 29, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Yasuyuki Nozuyama
  • Patent number: 7405085
    Abstract: An amorphous soft magnetic thin film material for forming shielding and keeper applications in MRAM devices. The amorphous soft magnetic material may be deposited using Physical Vapor Deposition (PVD) in the presence of a magnetic field, in order to form shielding layers and keepers in a multi-layer metallization process. The soft magnetic material may be an amorphous metallic alloy, such as CoZrX, where X may be Ta, Nb, Pd and/or Rh.
    Type: Grant
    Filed: September 15, 2004
    Date of Patent: July 29, 2008
    Assignee: Veeco Instruments, Inc.
    Inventors: Jacques Constant Stefan Kools, Ming Mao, Thomas Schneider, Jinsong Wang, Michael Gutkin
  • Patent number: 7405707
    Abstract: A composite antenna includes a first antenna structure and a second antenna structure integrally combined with the first antenna structure to operate under different frequency bands respectively that are used in different radio transmission systems such that the first antenna structure has a first conductive layer to operate under a first frequency band and the second antenna structure has a second conductive layer a thickness of which is thicker than that of the first conductive layer to operate under a second frequency band lower than the first frequency band.
    Type: Grant
    Filed: August 17, 2006
    Date of Patent: July 29, 2008
    Assignee: Toshiba Tec Kabushiki Kaisha
    Inventors: Nobuo Murofushi, Kouichi Sano, Yasuhito Kiji, Yasuo Matsumoto
  • Patent number: 7405027
    Abstract: Methods of preparing a liquid electrographic toner composition are provided, wherein a polymeric binder comprising at least one amphipathic copolymer comprising one or more S material portions and one or more D material portions is first prepared in a hydrocarbon reaction solvent, wherein the hydrocarbon reaction solvent comprises less than about 10% aromatic components by weight and has a Kauri-Butanol number less than about 30 mL. Toner particles are then formulated in the hydrocarbon reaction solvent and dried. The dried toner particles are then redispersed in a carrier liquid that is different from the reaction solvent, wherein the carrier liquid comprises less than about 10% aromatic components by weight and has a Kauri-Butanol number less than about 30 mL, to form a redispersed liquid electrographic toner composition. Preferred carrier liquids are silicone oils. Products and kits are also provided.
    Type: Grant
    Filed: October 31, 2004
    Date of Patent: July 29, 2008
    Assignee: Samsung Electronics Company
    Inventors: Hsin Hsin Chou, Jiayi Zhu, James A. Baker, A. Kristine Fordahl
  • Patent number: 7406047
    Abstract: A method of computing shortest paths in a weighted graph having vertices and an adjacency matrix with memory resources and a processor including (a) selecting integer weights; (b) carrying out a series of incrementations, an incrementation including finding a set of vertices to which one may arrive from a given set of vertices; (c) carrying out a series of decrementations, a decrementation including finding a set of vertices from which one may go to arrive to a given set of vertices; (d) causing the incrementations and decrementations to be carried out in any order; (e) transforming vectors of increments/decrements in paths, the paths making up a set E1 of the shortest paths in term of number of arcs or using a given number of arcs, Na; (f) selecting n-uple of paths C of lowest cost among set of paths E1; (g) calculating Nb=Na+1; (h) computing iteratively, while Nb?W(C) the following steps: i.
    Type: Grant
    Filed: May 19, 2004
    Date of Patent: July 29, 2008
    Assignee: KoDe
    Inventor: Michel Koskas
  • Patent number: 7404433
    Abstract: A liquid cooled heat sink includes: a casing defining an inner space and provided with a partitioning wall dividing the inner space into upper and lower chambers and formed with a fluid passage in fluid communication with the upper and lower chambers, the casing being formed with a fluid inlet in fluid communication with the upper chamber and adapted to be connected to an external cooling device; a fin unit provided in the lower chamber; and a pump mounted on the casing and having a suction end disposed in the upper chamber, extending through the partitioning wall, and in fluid communication with the lower chamber, and a discharging end disposed in the upper chamber and adapted to be connected to an external cooling device.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: July 29, 2008
    Assignee: Man Zai Industrial Co., Ltd.
    Inventors: Jen-Lu Hu, Hao-Hui Lin, Tsung-Ching Sun
  • Patent number: 7402566
    Abstract: A potent peptide inhibitor (SuperSog) of TGF-? family growth factor signaling, peptide variants thereof and nucleotide coding sequences therefore are provided by the invention. The Super-Sog peptide comprises a fragment of the Drosophilia short gastrulation (Sog) gene which includes the CR-1 cysteine-rich repeat of Sog. Methods and compositions for use of Super-Sog in therapeutic and diagnostic applications are also provided.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: July 22, 2008
    Assignee: The Regents of the University of California
    Inventors: Ethan Bier, Kweon Yu
  • Patent number: 7403418
    Abstract: A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: July 22, 2008
    Assignee: Silicon Storage Technology, Inc.
    Inventors: Ya-Fen Lin, Elbert Lin, Hieu Van Tran, Jack Edward Frayer, Bomy Chen
  • Patent number: 7404172
    Abstract: The present invention is a systematic and data-driven-decomposition (DDD) method and apparatus for use in VLSI synthesis. The invention decomposes a high level program circuit description into a collection of small and highly concurrent modules that can be implemented directly into transistor networks. This enables an automatic implementation of a decomposition process currently done by hand. Unlike prior art syntax-based decompositions, the method of the present invention examines data dependencies in the process' computation, and then attempts to eliminate unnecessary synchronization in the system. In one embodiment, the method comprises: a conversion to convert the input program into an intermediate Dynamic Single Assignment (DSA) form, a projection process to decompose the intermediate DSA into smaller concurrent processes, and a clustering process that optimally groups small concurrent processes to make up the final decomposition.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: July 22, 2008
    Assignee: California Institute of Technology
    Inventors: Catherine G. Wong, Mika Nystroem, Alain J. Martin
  • Patent number: 7402111
    Abstract: A rocking horse has a stand that includes a base portion with four tubular columns. The columns each have a tubular wall defining an interior. The wall has a top end with a top rim defining a top opening to the interior. An anchor pin extends through the wall and into the interior so that the pin engages two separated locations on the tubular wall. An S-shaped hook has a first end directly attached to the pin within the interior of the tubular wall and a second end extending out of the top opening on each column. The rocking horse also has four resilient members with outer ends connected to the second ends of the hooks, and inner ends connected to the toy horse for suspending the toy horse from the columns.
    Type: Grant
    Filed: April 26, 2006
    Date of Patent: July 22, 2008
    Assignee: Radio Flyer Inc.
    Inventors: Frederick Michelau, Thomas Schlegel
  • Patent number: 7401719
    Abstract: A staple-driving gun includes a gun body having a hollow housing configured with first and second air chambers separated by a partition, and a staple-discharging member mounted on the housing. A piston unit includes an operating member connected fixedly to a sleeve disposed movably in the first air chamber, and a piston rod disposed movably in the sleeve. The operating member is operable so as to move a valve end portion of the sleeve away from the partition such that compressed air flowing from the first air chamber into the second air chamber via a valve hole in the partition urges the piston rod to move toward the staple-discharging member for staple discharging. A biasing member biases the sleeve to a standby position, where the valve end portion of the sleeve seals the valve hole in the partition.
    Type: Grant
    Filed: March 1, 2006
    Date of Patent: July 22, 2008
    Assignee: Panrex Industrial Co., Ltd.
    Inventor: Chen-Ho Ou
  • Patent number: 7402407
    Abstract: Methods are provided for determining the position of a post-translationally modified (PTM) amino acid residue such as a phosphorylated amino acid residue or an O-glycosylated amino acid residue in a peptide. Also provided are methods for determining the identity of a PTM amino acid residue in a peptide. In addition, kits for practicing such methods are provided.
    Type: Grant
    Filed: September 10, 2004
    Date of Patent: July 22, 2008
    Assignee: California Institute of Technology
    Inventor: Gary M. Hathaway
  • Patent number: 7401560
    Abstract: A running board for railway car features a plank and a support where the support is constructed of a steel that is thicker than the steel of the plank. The support features flanges with mounting holes by which it is mounted to the railway car. As a result, the lives of the mounting areas of the support match the life of the plank so that the life of the running board is extended. The plank features side vertical and horizontal lip portions that extend from opposite side edges of the plank's anti-slip walkway. The horizontal lip portions are engaged by tabs formed in the support so that the plank is securely held to the support.
    Type: Grant
    Filed: May 19, 2005
    Date of Patent: July 22, 2008
    Assignee: GS Metals Corp.
    Inventor: Terry A. McCrary
  • Patent number: 7400656
    Abstract: There is provided a time stamp correction apparatus for being used in an apparatus which receives a packet including real time data and a time stamp based on network time from a network and reproduces the real time data on the basis of the time stamp, the time stamp correction apparatus including: receiving a first packet including the real time data and a first time stamp; successively generating the network time according to synchronous information input from the network; calculating a difference between time by the first time stamp and the network time; successively generating local time; generating a second time stamp based on the difference and the local time; generating a second packet by adding the second time stamp to the real time data; storing the generated second packet into a buffer unit; and conducting output control on the second packet on the basis of the local time.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: July 15, 2008
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Koguchi
  • Patent number: D573423
    Type: Grant
    Filed: March 3, 2006
    Date of Patent: July 22, 2008
    Assignee: Argyle Wine Tools Pty Ltd
    Inventor: Danny Simons