Abstract: To be able to recover from modes in which the oscillation of the voltage-controlled oscillator (V0) stops, the phase/frequency control circuit includes an RS flip-flop (RS) connected via two AND gates (U3, U3) to the two outputs (A1, A2) of the phase discriminator (P), which provide pulses for raising and lowering, respectively, the frequency of the voltage-controlled oscillator (V0). When the frequency/phase control circuit is out of lock, a pulse is generated with two monostable multivibrators (M1, M2) which passes through a signal selection circuit (S1) associated with the Q output of the RS flip-flop or through a signal selection circuit (S2) associated with the Q output of this flip-flop and controls the constant-current source (Q1) charging the smoothing device (G) or the constant-current source (Q2) discharging this device in such a way that the unwanted mode can be stopped by changing the control voltage of the oscillator (V0).

Abstract: A component-insertion table is provided with a receptacle (take-up device) for the circuit carrier, a programmable adhesive dosing feeder and a programmable component dispensing unit. The receptacle containing the circuit carrier is moved coordinately below a cover of the component-insertion table to a centrally located position for the automatic application of an adhesive with the aid of the adhesive dosing feeder, as well as into a centrally located insertion position for the manual placement of the components. The adhesive-application position and the insertion position be within a window in the cover through which the individual component insertion locations on the circuit carrier are made from above in a programmed order of succession.

Abstract: A device is described which operates as a "mechanical fuse" in a guy arrangement such that when loading forces on the guyed structure exceed a predetermined level, the device will add length to the guy arrangement. The device includes two plates coupled by a hinge bolt and a shear bolt. When the force exceeds the predetermined level, the shear bolt is severed by the plates allowing the plates to "scissors" open about the hinge bolt.

Abstract: In the process according to the invention, in addition to the conventional two photoresist processes for opening the contact holes and for manufacturing the interconnecting pattern, two photoresist processes are used with one photoresist mask each for manufacturing the regions of the planar transistor. Without additional photoresist masks, further semiconductor components, such as integrated resistors and/or lateral transistors are capable of being manufactured. The process is characterized by the fact that, the first photoresist mask is used to manufacture a diffusion masking layer which leaves the base area of the planar transistor unmasked. In this area, the dopings of the collector region are introduced into the substrate and the collector region is diffused. Thereafter, at a relatively small dose rate, there is carried out an implantation of dopings of the base region.

Abstract: The invention provides a digital circuit for generating a binary signal output when a predetermined frequency ratio, v=f1/f2, of two signals F1 and F2 occurs during a selected measuring period. The circuit is particularly adapted for use in a color television receiver to determine the ratio between the chrominance-subcarrier frequency and the horizontal frequency, which ratio is fixed at the transmitting end, both in the PAL system and the NTSC system.

Abstract: To prevent the separation-level shift occurring in the clamping circuit during the transmitted vertical synchronizing pulses or during prolonged interference pulses, a pulse opening an electronic switch (S) inserted between the clamping circuit and one RC section thereof is generated by means of a coincidence stage (KO), a gate circuit (TS), an inverter (I), and an AND gate (U). The clamping circuit is thus unblocked only during the horizontal synchronizing pulses, so that no shift of the separation level can occur during the vertical synchronizing pulses or during any interference pulses in the composite color signal (F).

Abstract: A frequency/phase locked loop for providing signals which are frequency and phase locked to signals at a reference frequency from a reference oscillator which is determinative of the frequency stability includes a frequency-controlled generator of a lower frequency stability. The frequency controlled generator is responsive to control signals for switching between first and second frequencies which are substantially higher than the reference frequency. The second frequency is approximately one to ten percent higher than the first frequency. The frequency divider coupled to the frequency generator provides an output signal at the same frequency as the reference oscillator. A digital phase comparator compares the outputs of the frequency divider with the reference signals.

Abstract: This invention provides a process for manufacturing a monolithic integrated solid-state circuit comprising at least one bipolar transistor (npn) and at least insulated-gate field-effect transistor (PMOS), in which the dopings of the regions (zones) (1, 4, 8; 2, 5, 6; 15, 16) are introduced into the one surface side of a semiconducting substrate (3) by employing photoresist masks and by way of ion implantation. Moreover, the process according to the invention makes use of an oxidation masking layer with a topmost disposed nitride layer, with the thickness and the composition thereof, either with or without the nitride layer, corresponding to the gate insulator layer.

Abstract: To generate a binary signal on the occurrence of a given frequency ratio of two signals, the higher-frequency, first signal is applied to the count input of a first up-counter whose maximum count is greater than the frequency ratio. The attainment of a count of the first up-counter in an upper range of successive counts which includes the frequency-ratio count and the maximum count is monitored by a decoder having an output for all range counts, an output for a count lying a few counts before the frequency-ratio count, and an output for the frequency-ratio count. The first of these outputs is coupled to the control input of an electronic make contact; the second output is coupled to the trigger input of a monostable multivibrator, and the third output is connected to one of the two signal inputs of an electronic switch having its other signal input connected to the output of the make contact.

Abstract: An electrically programmable memory includes a test circuit usable for detection of interaction between adjacent memory cells by easily permitting a checkerboard-pattern to be programmed into the memory.

Abstract: A volume control valve in accordance with the invention is formed in a valve body which is adapted for insertion into a valve fitting. The valve body includes a valve seat insert and a valve disk. A sealing element is disposed between the valve seat insert and the valve fitting. The sealing element is carried on a supporting piece such that a first face of the sealing element is disposed on one side of the supporting piece and a second face is disposed on the other side of the supporting piece. The supporting piece is held against shoulders in the body such that the valve seat insert is prestressed by a predetermined amount by the first face. The second face is deformable against the fitting to accomodate different fitting depths.

Abstract: A magnetic ring for adjusting color purity and convergence is secured to the electron gun of a color-picture tube. It encloses an oblong area which is perpendicular to the plane defined by the three electron beams produced by the electron gun. The shape of the magnetic ring is chosen so that the y-distance of the ring from the central axis of the central electron beam is greater than the distance of the ring from the respective central axis of an outer electron beam. This selection of distances influences the focus of the beams.

Abstract: Division by fractions is accomplished with a counter (Z) presettable to integers and a digitally adjustable delay line (V) following this counter. The fractional parts (b) of the divisor, which are held in decimal point representation (a+0.b) in a divisor register (R), are applied to a first adder (A1) followed by a buffer memory (S), and the integral parts (a) of this divisor are applied to a second adder (A2). The output of the buffer memory (S) is coupled to the set input (Es) of the delay line (V) and to the second input (E2) of the first adder (A1). Thus, at the input of the delay line (V), the number corresponding to the fractional parts (b) is continuously increased by the fractional parts (b) until the overflow output (Ao) of the first adder (A1) provides a signal which is applied to the least significant digit (LB) of the first input (E1) of the second adder (A2). One unit is thus added to the integral parts (a), and the counter (Z) counts one additional digit for one cycle.

Abstract: The interface circuit contains a single operational amplifier (OR, OG, OB) per chrominance channel, with a resistance network (WR, WG, WB) for white-level adjustment connected between the inverting input and the output of this amplifier. The output resistances of the matrix output amplifiers (MR, MG, MB) must be low, and a low-value resistor (RR, RG, RB) is connected between the output of each output amplifier and the noninverting input of each operational amplifier (OR, OG, OB). Video-signal, brightness-, blanking, and external-signal-control currents (ISR, ISG, ISB; IHR, IHG, IHB; IBR, IBG, IBB; IER, IEG, IEB) are applied to the non-inverting input of the respective operational amplifier.The control currents permit the white-level adjustment and the blanking-voltage adjustment to be made independently of each other and eliminate any interaction between brightness adjustment, blanking, and external-signal gating. Compared with prior art arrangements, a simpler circuit is obtained.

Abstract: A memory access and control circuit is described for use with a non-volatile memory matrix utilizing insulated gate field effect transistors. Two one out of n selector circuits which are complementary in operation and which are formed from transistors of opposite conductivity type are formed on an integrated circuit and transistors of one conductivity type are formed in insulating islands in the substrate.

Abstract: To digitally synchronize the chrominance-subcarrier oscillator in the form of a phase-locked loop with the color burst contained in the composite color signal, suitable digital subcircuits are provided. During the keying pulse, the digital R-Y and B-Y color-difference signals are accumulated line by line. The corresponding R-Y value is then added to a desired phase value or a tint-control value, and for deviations from the burst phase between +90.degree. and -90.degree., the sum signal, after being limited if necessary, is applied to a digital-to-analog converter, filtered in a low-pass filter, and then used to control the chrominance-subcarrier oscillator. If the phase deviations lie between +90.degree. and +180.degree. or -90.degree. and -180.degree., the digital-to-analog converter is constantly fed with the upper or the lower limit value, respectively, via a switching stage.

Abstract: In a circuit for selecting a random number (N) of potentials (Ui . . . ), which is integrated in accordance with the complementary insulated-gate field-effect transistor technique, one transmission gate (G . . . ) is associated with each potential, with the switching section of the gate lying between the potential (Ui . . . ) and the output (U), and the two control inputs of the respective transmission gate (G . . . ) are connected either directly or via a respectively associated inverter (I . . . ) to the corresponding output of a CMOS-1-ex-n-decoder. This decoder may consist of a 1-ex-n-open-circuit-decoder (SD) and of a 1-ex-n-short-circuit decoder (KD) whose address inputs are connected in pairs to one another and whose like outputs (1 . . . 8) are connected to one another. The open-circuit decoder (SD) consists of transistors (TP) of the one channel conductivity type, and the short-circuit decoder (KD) consists of transistors (TN) of the other channel conductivity type.

Abstract: Dopants in semiconductor bodies which have been deactivated during processing are reactivated by pulse heating the body to a temperature within the region in which the semiconductor sheet resistivity decreases with increasing anneal temperature. Typically this comprises raising the body to 1000.degree. C. within 40 seconds or less in an inert atmosphere and allowing it to cool immediately or within approximately 30 seconds. The heating is so rapid that diffusion side effects are minimized. Pulse heating may be achieved by means of a sealable microwave heating chamber (1) which can be pressurized or vented as desired and into which microwave energy is directed for a predetermined time. The microwave heating can also be employed for other processing, particularly high pressure oxidation of silicon.

Abstract: A rotary plug valve includes a rotary plug which has a relatively thin-walled valving portion. To lock the valve in position or to achieve leak tight closure of the valve, the rotary plug is subjected to pressure such that the wall of the thin-walled valving portion deflects outward to tightly contact the surrounding wall of the plug receiving cavity in the valve housing.

Abstract: To adjust time delays in equidistant steps, an inverter chain is provided with an even number of static inverters of identical topology. The output of one of the even-numbered inverters is connected to the signal output via a selector switch. During suitable frequency-measuring periods, an odd number of inverters is connected to form a ring by directly coupling the output of an odd-numbered inverter to the input of the first, and a digital measuring arrangement determines the time delay of the ring-connected portion from the frequency of the ring's self-excited oscillation. The output signal of the measuring arrangement is used to adjust the time delay of the inverter chain.