Abstract: A new optical lithographic exposure apparatus is described. The apparatus may comprise, for example, a lithographic stepper or scanner. A wafer stage comprises a means of supporting a semiconductor wafer. A mask stage comprises a means of holding a first mask and a second mask and maintaining a fixed relative position between the first mask and the second mask. The mask stage may further comprise an independent means of aligning each mask. A light source comprises a means to selectively shine actinic light through one of the first mask and the second mask. An imaging lens is capable of focusing the actinic light onto the semiconductor wafer. A step and scan method using the mask stage is provided. A first mask and a second mask are loaded into a mask stage of an optical lithographic exposure apparatus. The first mask and the second mask are aligned. The first mask is scanned. The wafer is then stepped. The second mask is scanned.

Abstract: A new software support package is provided that monitors tool status and scheduling requirements in a semiconductor manufacturing environment. A multiplicity of tools interfaces with a Manufacturing Execution system (MES) that is a functional component of the Operation and supervision integrated MES user Interface (OMI). A User Interface (UI) function, which is also part of the OMI, interfaces between a multiplicity of users (of the OMI functions) and the MES sub-component of the OMI system.

Abstract: A new method of detecting a reticle option layer in an integrated circuit device has been achieved. The method may be applied to detect the presence of the threshold voltage implantation reticle option layer by direct die probing or by probing a pin of a package integrated circuit. The current through a first MOS transistor is measured by forcing a test voltage on the drain and the gate. The gate and the drain of the first MOS transistor are connected together while the source is connected to a reference voltage. The first MOS transistor has the standard threshold implantation but not the threshold voltage reticle option. The current through a second MOS transistor is measured by forcing the same test voltage on the drain and the gate. The gate and said drain of the second MOS transistor are connected together while the source is connected to a reference voltage. The second MOS transistor has the standard threshold voltage implantation and the threshold voltage implantation reticle option layer.

Abstract: A new electrostatic discharge protection device is achieved. A p-well region is in a semiconductor substrate. An n+ region in the p-well region is connected to a first voltage supply. An n-well region in the p-well region is spaced from the n+ region such that a depletion region will extend therebetween during normal operation. A p+ region in the n-well region is connected to a second voltage supply of greater value than the first voltage supply during normal operation. Current is conducted through the n+ region to the p+ region during an electrostatic discharge event.

Abstract: A new method of fabricating solder bumps in the manufacture of an integrated circuit device has been achieved. Contact pads are provided overlying a semiconductor substrate. A passivation layer is provided overlying the contact pads. The passivation layer has openings that expose a top surface of the contact pads. A sacrificial layer is deposited overlying the passivation layer and the exposed top surface of the contact pads. The sacrificial layer is not wettable to solder. Under bump metallurgy (UBM) caps may be formed either by deposition and patterning of a UBM layer stack or by selective electroless deposition of a material such as nickel and gold. An aperture mask is formed overlying the sacrificial layer. The aperture mask has openings that expose a part of the sacrificial layer overlying the contact pads. A solder layer is printed into the openings in the aperture mask. The solder layer is reflowed to form solder bumps overlying the contact pads. The aperture mask is stripped away.

Abstract: A new digital follower device is achieved. The digital follower device comprises an n-channel vertical FET device and a p-channel vertical FET device. Each vertical FET device comprises a bulk region in a semiconductor substrate. The bulk region comprises a first doping type. A STI region is in the bulk region. A drain region is on a first side of the STI region. The drain region overlies the bulk region. The drain region comprises the first doping type. A gate region is on a second side of the STI region. The gate region comprises the first doping type. A voltage on the gate region controls a vertical channel in the bulk region. A buried region is between the gate region and the bulk region. The buried region comprises a second doping type. The n-channel FET device drain and the p-channel FET device drain are connected together. The n-channel FET device, gate and the p-channel FET device gate are connected together.

Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A tunneling oxide layer is formed overlying a semiconductor substrate. A first polysilicon layer, an interpoly oxide layer and then a second polysilicon layer are deposited. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions that are deeper and less abrupt than the drain junctions.

Abstract: An energy control circuit for a class D amplifier is achieved. The energy control circuit comprises, first, a means of generating an energy accumulation signal proportional to an output drive signal of the class D amplifier. Last, a means of receiving the energy accumulation signal and of interrupting the output drive signal when the energy accumulation signal exceeds a reference level. Single-ended and H-bridge amplifiers are achieved.

Abstract: A method to form a closely-spaced, vertical NMOS and PMOS transistor pair in an integrated circuit device is achieved. A substrate comprise silicon implanted oxide (SIMOX) wherein an oxide layer is sandwiched between underlying and overlying silicon layers. Ions are selectively implanted into a first part of the overlying silicon layer to form a drain, channel region, and source for an NMOS transistor. The drain is formed directly overlying the oxide layer, the channel region is formed overlying the drain, and the source is formed overlying the channel region. Ions are selectively implanted into a second part of the overlying silicon layer to form a drain, channel region, and source for a PMOS transistor. The drain is formed directly overlying the oxide layer, the PMOS channel region is formed overlying the drain, and the source is formed overlying the channel region. The PMOS transistor drain is in contact with said NMOS transistor drain.

Abstract: A new method to form a LVT-SCR device in the manufacture of an integrated circuit device is achieved. The method comprises providing a SOI substrate comprising a silicon layer overlying a buried oxide layer. The silicon layer further comprises a first well of a first type and a second well of a second type. First and second doped regions of the first type are formed. The first doped region is in the first well. The second doped region is in the second well and forms an anode. Third, fourth, and fifth doped regions of the second type are formed. The third and fourth doped regions are in the first well. The fifth doped region is partly in the first well and partly in the second well. The first and third doped regions form a cathode. First and second gates are formed overlying the silicon layer. The first gate is between the third and fourth doped regions. The second gate is between the fourth and fifth doped regions. The doped regions are not separated by isolation oxide.

Abstract: A method is provided for turning off MOS transistors through an anti-code (type) LDD implant without the need for high energy implant that causes poly damage. The method also negates any deleterious effects due to the variations in the thickness of the poly gate. The anti-code LDD implant can be performed vertically, or at a tilt angle, or in a combination of vertical and tilt angle. The method can be made part of a Flash-ROM process that is applicable to both polycide and silicide processes.

Abstract: A method is provided for forming a highly dense stacked gate flash memory cell with a structure having multi floating gates that can assume 4 states and, therefore, store 2 bits at the same time. This is accomplished by providing a semiconductor substrate having gate oxide formed thereon, and shallow trench isolation and a p-well formed therein. A layer of nitride is next formed over the substrate and an opening formed therein. Polysilicon floating gate spacers are formed in the opening. A dielectric layer is then formed over the floating gates followed by the forming of a control gate. The adjacent nitride layer is then removed leaving a multi-level structure comprising a control gate therebetween multi floating gates with the intervening dielectric layer.

Abstract: The polishing of a layer of boro-phosphate-silicate-glass (BPSG) is not easy to control as a result of CMP slurry chemistry effects, the doping concentration of the layer of BPSG and the heat treatment to which the layer of BPSG has been submitted prior to the process of CMP. The invention has developed a CMP endpoint detection mode that minimizes variations of the process of CMP of a layer of BPSG by these factors. An endpoint detection algorithm has been developed, which has been applied and has proven to significantly improve a statistical measure, which reflects the process deviation from the process mean for the process of CMP of a layer of BPSG.

Abstract: A battery protection circuit for use between a battery output and a load is achieved. The circuit comprises, first, a plurality of fused cells coupled in parallel between the battery output and the load. Each fused cell comprises, first, a fuse having first and second terminals where the first terminal is coupled to a battery output. Second, a means having zener effect has a p terminal and an n terminal. The p terminal is coupled to the second terminal of the fuse. Finally, a cell switch having first and second terminals completes each fused cell. The cell switch first terminal is coupled to the second terminal of the fuse, and the cell switch second terminal is coupled to the n terminal of the diode to form a cell output. Finally, the battery protection circuit comprises a shorting switch, that may comprise a MOS transistor that exhibits punch through, that is coupled between the load and each fused cell output. The current source second terminal is coupled to ground.

Abstract: A new floating gate programmable device cell is achieved. The device comprises, first, a negative injection transistor having drain, source, bulk, and gate. The source and bulk are coupled to ground. The drain forms an output of the cell. A positive injection transistor has drain, source, bulk, and gate. The drain, source, and bulk are coupled to a programming voltage. The gate is coupled to the negative injection transistor gate to form a floating gate node. Finally, a capacitor has a first terminal coupled to the floating gate node and a second terminal coupled to a control voltage. The states of the programming voltage and the control voltage determine negative charge injection onto the floating gate node and positive charge injection onto the floating gate node. A voltage on the floating gate node comprises a nonvolatile memory state that is detectable by the impedance of the output.

Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.

Abstract: A method is disclosed for forming dual damascene structures with a multi-purpose composite mask. The composite mask serves not only to prevent via poisoning, but also to improve the lithographic characteristics of forming a dual damascene structure. This is accomplished by using a mask comprising silicon-based as well as polymeric dielectric layers. Thus, one of the components of the composite mask, namely, the polymeric dielectric, makes it possible to protect the via openings by conformally covering the sidewalls of the via and, at the same time, by bringing controllability to the height of the protective dielectric in the via opening. In addition, because the polymeric dielectric also serves as the main plasma resisting layer during the trench etch, the required photoresist is much thinner; therefore, the lithography process window can be extended beneficially.

Abstract: A memory cell device is achieved. The memory cell device comprises a first transistor having gate, drain, and source. A second transistor has gate, drain, and source. The first transistor drain is coupled to an array bit line. The second transistor source is coupled to an array source line. The first transistor source is coupled to the second transistor drain. The first transistor and the second transistor comprise one Flash transistor and one mask ROM transistor. The programmed state of the mask ROM transistor can be read.

Abstract: A thin film semiconductor die circuit package is provided utilizing low dielectric constant (k) polymer material for the insulating layers of the metal interconnect structure. Five embodiments include utilizing glass, glass-metal composite, and glass/glass sandwiched substrates. The substrates form the base for mounting semiconductor dies and fabricating the thin film interconnect structure.

Abstract: A new battery charging, discharging, and protection circuit is achieved. The circuit comprises, first, a FET switch having gate, source, drain, and bulk. The FET switch may comprise either a NMOS device or a PMOS device. The source is coupled to a load terminal, and the drain is coupled to a battery terminal. Second, a means of controlling the FET switch gate and the bulk is included. The FET switch gate voltage determines the OFF and ON state of said FET switch. The bulk is switchably coupled between the battery terminal and the load terminal. A cascaded version is disclosed.