Abstract: A new Flash memory cell device with a parasitic surface transfer transistor (PASTT) and a method of manufacture are achieved. The device comprises, first, a semiconductor substrate. The semiconductor substrate further comprises an active area and an isolation barrier region. A source junction is in the active area. A drain junction is in the active area. A cell channel is in the active area extending from the drain junction to the source junction. A parasitic channel is in the active area on the top surface of the semiconductor substrate extending from the drain junction to the source junction. The parasitic channel is bounded on one side by the isolation barrier region and on another side by the cell channel. A floating gate comprises a first conductive layer overlying the cell channel with a tunneling oxide layer therebetween. The floating gate does not overlie the parasitic channel.

Abstract: A new high voltage, high side driver circuit has been achieved. The circuit comprises, first, a top PFET having gate, drain, source, and bulk. The gate is coupled to a switching signal. The source is coupled to a high voltage. Second, a top resistor has first and second terminals. The first terminal is coupled to the high voltage. Third, a middle PFET cell comprises a middle PFET having gate, drain, source, and bulk. The source is coupled to the top PFET drain. The gate is coupled to the top resistor second terminal. A middle resistor has first and second terminals. The first terminal is coupled to the middle PFET gate. Finally, a middle means of claimping the middle PFET gate and a clamping voltage completes the middle PFET cell. Fourth, a bottom PFET cell comprises, first, a bottom PFET having gate, drain, source, and bulk. The gate is coupled to the middle resistor second terminal, the source is coupled to the middle PFET drain, and the drain forms a high side driver output.

Abstract: A new current reference circuit is achieved. This current reference circuit is based on MOS transistors but does not depend upon the threshold voltage. The circuit comprises, first, a first MOS transistor having gate, drain, and source. A gate voltage value is coupled from the gate to the source. A second MOS transistor has gate, drain, and source. The second MOS transistor is of the same size and type as the first MOS transistor. The source is coupled to said first MOS transistor source. The gate voltage value plus a delta voltage value is coupled from the gate to the source. A means is provided for forcing a drain voltage value from the drain to the source of the first MOS transistor and from the drain to the source of the second MOS transistor. The first MOS transistor and the second MOS transistor conduct drain currents in the linear mode.

Abstract: A method to form a combined enclosure and heat sink structure for a semiconductor device is achieved. A first feedstock comprising a first mixture of powdered metal materials, lubricants, and binders is prepared. A second feedstock comprising a second mixture of powdered metal materials, lubricants, and binders is prepared such that the difference between the sintering shrinkage of each of the first and second feedstocks is less than 1%. The first and second feedstocks are pressed to form a first green part having an enclosure shape and a second green part having a heat sink shape. The lubricants and the binders from said first and second green parts are removed to form a first powdered skeleton and a second powdered skeleton. The first and second powdered skeletons are sintered to complete the combined enclosure and heat sink structure. The first and second powdered skeletons are in intimate contact during the sintering.

Abstract: A method to form a very low resistivity interconnection in the manufacture of an integrated circuit device is achieved. A bottom conductive layer is formed overlying a substrate. The bottom conductive layer creates a first electrical coupling of a first location and a second location of the integrated circuit device. A dielectric layer is formed overlying the bottom conductive layer. A top conductive layer is formed overlying the dielectric layer. The top conductive layer is coupled to the bottom conductive layer through openings in the dielectric layer to form a second electrical coupling of the first location and the second location. A metal wire is bonded to the top conductive layer to form a third electrical coupling of the first location and the second location to complete the very low resistivity interconnection in the manufacture of the integrated circuit device.

Abstract: A multiple time programmable (MTP) memory device is achieved. The device comprises, first, a memory cell array including a means of electrical erasability and electrical programmability. The memory cell array comprises, preferably, a Flash memory cell array. A package has an external pin configuration that conforms to the JEDEC standard for an EPROM device wherein an external, positive programming voltage (VPP) pin is provided. Finally, an external, negative erasing voltage (VNN) pin is provided. The VNN pin is, preferably, multiplexed with the chip enable bar (CEB) pin.

Abstract: A new level shifting circuit, using a zero threshold voltage device, is described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter has input connected to the input of the level shifting circuit and output forming an inverted level shifting input. A first NMOS transistor has the gate connected to the level shifting input and the source connected to ground. A first zero threshold NMOS transistor has the gate connected to a low bias voltage and the source connected to the first NMOS transistor drain. A first PMOS transistor has the gate connected to the level shifting output, the source connected to the high supply, and the drain connected to the first zero threshold NMOS transistor drain. A second NMOS transistor has the gate connected to the inverted level shifting input and the source connected to ground.

Abstract: A method to form contacts in an integrated circuit device comprising to eliminate shorting between adjacent contacts due to dielectric layer voids is achieved. A substrate is provided. Narrowly spaced conductive lines are provided on the substrate. A dielectric layer is deposited overlying the conductive lines and the substrate. The dielectric layer is etched through to the top surface of the substrate in areas defined by lithographic mask to form contact openings between adjacent narrowly spaced conductive lines. An insulating layer is deposited overlying the dielectric layer and filling the contact openings wherein the insulating layer forms a lining layer inside the contact openings and fills any voids in the dielectric layer extending out of the contact openings. The insulating layer is etched through to expose the top surface of the substrate. A conductive layer is deposited overlying the dielectric layer and filling the contact openings. The conductive layer is etched as defined by lithographic mask.

Abstract: A new current sense circuit is achieved. The circuit comprises, first, an output transistor having gate, source, and drain. The drain is coupled to a load, the source is coupled to a power rail, the gate is coupled to a control voltage such that the output transistor conducts an output current. Second, a sense transistor has gate, source, and drain. The source is coupled to the power rail and the gate is coupled to the control voltage. A sensing factor comprises the output transistor size divided by the sense transistor size. Third, a means of equalizing the sense transistor drain-to-source voltage and the output transistor drain-to-source voltage is used such that the sense transistor drain current comprises the output current divided by the sensing factor. Finally, a current controlled oscillator is included. The current controlled oscillator has input and output. The input comprises the sense transistor drain current.

Abstract: A new linearized transconductance circuit for converting an input into an output has been achieved. This linearized transconductance circuit is especially suited for application in a mixing circuit using a double-balanced cell. The circuit allows optimization of linearity and noise figure without excessive current. The input comprises first and second phases having a differential voltage therebetween. The output comprises first and second phases having a differential current therebetween that is proportional to the differential voltage. The circuit comprises, firstly, first, second, third, and fourth MOS transistors, with each transistor having a gate, a drain, and a source. The gates of the first and third MOS transistors are coupled to the input first phase. The drains of the first and third transistors are coupled to the output first phase. The gates of the second and fourth MOS transistors are coupled to the input second phase.

Abstract: A method of forming shallow junction MOSFETs is achieved. A gate oxide layer is formed overlying a substrate. A first electrode layer, of polysilicon or metal, is deposited. A silicon nitride layer is deposited. The silicon nitride layer and the first electrode layer are etched through to form temporary MOSFET gates. Ions are implanted into the substrate to form lightly doped junctions. A spacer layer is deposited. The spacer layer and the gate oxide layer are anisotropically etched to form sidewall spacers. Ions are implanted into the substrate to form heavily doped junctions. The silicon nitride layer is etched away. A second electrode layer, of polysilicon or metal, is deposited overlying the substrate, the sidewall spacers, and the first polysilicon layer. The second electrode layer is polished down to the top surfaces of the sidewall spacers to complete the MOSFETs and to form permanent gates and conductive connections to the source and drain junctions.

Abstract: A minimum pulse width detection and regeneration circuit is achieved. The circuit includes, first, a pulse width detector capable of detecting if an input signal pulse is within a range between a minimum width and a maximum width. Second, a pulse width extender is capable of extending the input signal pulse width to the maximum width if the input signal pulse is in the range. Finally, a glitch filter is capable of filtering out the input signal pulse if the input signal pulse is less than the minimum width.

Abstract: A new method of electroless plating a metal layer onto a semiconductor substrate in the manufacture of an integrated circuit device has been achieved. A semiconductor substrate is provided. A metal layer is electroless plated onto the semiconductor substrate. Light is shielded from the semiconductor substrate to thereby eliminate the photoelectric effect in the semiconductor substrate during the electroless plating. A new apparatus for electroless plating a metal layer onto a semiconductor substrate is achieved. The apparatus comprises, first, an electroless plating tank capable of holding an electroless plating solution. The sidewalls and bottom of said electroless plating tank prevent light intrusion into the electroless plating solution during a plating process. Second, a wafer fixture capable of suspending a semiconductor substrate wafer in the electroless plating solution in the electroless plating tank during the plating process is provided.

Abstract: A new MOS varactor device is described. A bottom electrode comprises a plurality of diffusion junctions in a semiconductor substrate. The semiconductor substrate may be n-type or p-type. The diffusion junctions are arranged in a two-dimensional array. The diffusion junction may be either n-type or p-type. The diffusion junctions may be contained in a p-well or an n-well. A dielectric layer overlies the semiconductor substrate. A top electrode overlies the dielectric layer. The top electrode comprises a single polygon containing a two-dimensional array of openings therein that exposes the diffusion junctions. The top electrode preferably comprises polysilicon. An interlevel dielectric layer overlies the top electrode and the diffusion junction. The interlevel dielectric layer has a two-dimensional array of contact openings that expose the underlying diffusion junctions. A patterned metal layer overlies the interlevel dielectric layer and contacts the diffusion junctions through the contact openings.

Abstract: A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.

Abstract: A pseudo SRAM integrated circuit device is achieved. The device comprises, first, a memory array comprising a plurality of dynamic storage cells. Finally, an access controller is included. The access controller provides read and write access to the memory array from an external device. The access controller performance is compatible with a standard SRAM memory device. The access controller enables a partial data retention mode comprising selective refreshing of at least one part of the memory array and non-refreshing of at least one other part of the memory array.

Abstract: A new method of forming MOS transistors with self-aligned silicide has been achieved. A gate oxide layer is formed overlying a semiconductor substrate. A polysilicon layer is deposited. The polysilicon layer and the gate oxide layer are patterned to form gates. Ions are implanted to form lightly doped drain regions. A dielectric layer is deposited. The dielectric layer is polished down to expose the top surface of the gates. The dielectric layer is then anisotropically etched down to form dielectric sidewall spacers. The dielectric sidewall spacers cover a portion of the vertical sidewalls of the gates while exposing a portion of the vertical sidewalls of the gates. Ions are implanted to form source and drain regions. A metal layer is deposited. Contact surfaces are formed between the metal layer with: the exposed top surfaces of the gates, the exposed portions of the vertical sidewalls of the gates, and the exposed source and drain regions.

Abstract: A new method of fabricating a stacked gate Flash EEPROM device having an improved stacked gate topology is described. Isolation regions are formed on and in a semiconductor substrate. A tunneling oxide layer is provided on the surface of the semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. The first polysilicon layer is polished away until the top surface of the polysilicon is flat and parallel to the top surface of the semiconductor substrate. The first polysilicon layer is etched away to form the floating gate. The source and drain regions are formed within the semiconductor substrate. An interpoly dielectric layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly dielectric layer. The second polysilicon layer and the interpoly dielectric layer are etched away to form a control gate overlying the floating gate. An insulating layer is deposited overlying the oxide layer and the control gate.

Abstract: New level shifting circuits, one using dynamic current compensation and one using dynamic voltage equalization, are described. An input swings between a low supply and ground. An output swings between a high supply and ground. An inverter input is connected to the input of the level shifting circuit to form an inverted level shifting input. A first NMOS transistor has the gate tied to the level shifting input and the source tied to ground. A first PMOS transistor has the gate tied to the level shifting output, the source tied to the high supply, and the drain tied to the first NMOS drain. A second NMOS transistor has the gate tied to the inverted level shifter input, the source tied to the ground, and the drain tied to the level shifting output. A second PMOS transistor has the gate tied to the first NMOS drain, the source tied to the high supply, and the drain is tied to the level shifting output.

Abstract: A new method of forming a metal oxide high dielectric constant layer in the manufacture of an integrated circuit device has been achieved. A substrate is provided. A metal oxide layer is deposited overlying the substrate by reacting a precursor with an oxidant gas in a chemical vapor deposition chamber. The metal oxide layer may comprise hafnium oxide or zirconium oxide. The precursor may comprise metal alkoxide, metal alkoxide containing halogen, metal &bgr;-diketonate, metal fluorinated &bgr;-diketonate, metal oxoacid, metal acetate, or metal alkene. The metal oxide layer is annealed to cause densification and to complete the formation of the metal oxide dielectric layer in the manufacture of the integrated circuit device. A composite metal oxide-silicon oxide (MO2-SiO2) high dielectric constant layer may be deposited using a precursor comprising metal tetrasiloxane.