Abstract: A core includes a tubular body for supporting a wound sheet roll on a spindle. The body includes an annular outer surface for receiving the sheet roll, and an annular inner surface defining a bore for receiving the spindle. A plurality of ribs project inwardly from the body inner surface and extend axially between opposite first and second openings for nesting in the corresponding slots in the spindle. Each of the ribs includes a beveled fork for frictionally engaging a corresponding one of the spindle slots to frictionally retain the core axially thereon.

Abstract: A method of displaying a video image in a computer which has the ability to simultaneously display multiple windows. A graphics image is displayed in a first window, and a video image is displayed in a second window having controls for annotating the graphics image in the first window.

Abstract: A work station which includes a central processing unit (CPU), first and second interface chips connected to respective external or peripheral units, and a local bus connected to the CPU and chips and adapted for multiple byte data communication between the CPU and chips. First and second one-byte registers are included in the first and second chips, respectively, and are simultaneously accessible by the CPU.

Abstract: A computer memory system connectable to a processor and having programmable operational characteristics based on characteristics of the processor. The memory system includes several caches and a main memory connected to a bus. One cache can be programmed to store only code data. Another cache can be programmed to buffer data writes to the main memory only from the processor. The main memory supports fast page mode and can be programmed to selectively reopen either code or non-code data pages.

Abstract: A statistically fast, high performance computer memory system including a system memory for storing code and non-code data accessible by at least two bus masters, a bus connecting the memory with the bus masters, and a plurality of caches connected to the bus. An internal cache holds data selected solely on the basis of memory accesses by the host processor, a pre-fetch cache pre-fetches code from the memory, and a write buffer cache connected to the bus for buffering data written to the memory.

Abstract: A method and system for managing data elements in a memory system. The memory system is accessible by a plurality of bus masters connected by a bus to the system. Code data elements to be read are predicted. The predicted code data elements are then transferred within the memory system from a slow to high speed memory without delaying memory access requests for data from the bus masters.

Abstract: A scan-based logic test apparatus is provided for use with an automated test equipment (ATE) digital tester which tests scan-based logic IC devices. The test apparatus is embodied in a test card which is pluggable into a bus slot within a computer. The computer includes a permanent memory for storing scan-based pattern data including serial input pattern data and expected serial output pattern data. The test card includes an I/O interface control which interfaces the test card to the computer to permit retrieval of the scan-based pattern data from the permanent memory and which interfaces the test card to the digital tester to permit the tester to supply control signals to the test card. The test card further includes an SRAM memory which is coupled to the I/O interface control. The SRAM memory stores the scan-based pattern data including serial input pattern data and expected serial output pattern data upon retrieval thereof from the permanent memory by the I/O interface control.

Abstract: An interface circuit and method for transferring data between first and second buses. The circuit includes a buffer having a plurality of registers and write and read means. The write means stores data words received from the second bus in non-sequential registers. The read means transfers the data words from sequential registers to the first bus.

Abstract: A semiconductor fuse and method for fabricating the same An insulating layer is provided and a trench formed therein. A fusible link is then formed across the insulating layer and trench and conformal therewith. The link has a break region of minimum thickness and width at an intersection of a sidewall and bottom surface of the trench.

Abstract: A DMA controller is connected to a CPU in a work station. The controller includes a multiple byte memory address register (MAR), and a pointer register connected between the CPU and MAR. The pointer register is responsive to a command from the CPU to give the CPU successive access to the byte positions of the MAR for writing a memory address thereto. The DMA controller may also include a single byte register associated with the pointer register and connected between the CPU and MAR. The CPU writes an address to the MAR one byte at a time via the single byte register. Preferably, the MAR has a capacity of four 8 bit bytes.

Abstract: The invention concerns the simultaneous display of video data and text data on a computer display. The invention stores both types of data in display memory. Transition codes mark the separation between the two types. The invention converts each type of data into signals which a CRT display can understand. The invention changes the type of conversion, as appropriate, when transition codes are reached.

Abstract: An architecture and method for operating a work station. The work station includes a CPU, a bus interface unit and a control line. The CPU is selected from a group of CPUs differing in certain operational parameters. The bus interface circuit is connected between an external bus and the CPU. The control line is connected to the interface circuit and provides a signal indicating the type of CPU connected to the circuit.

Abstract: The invention is a system and method for accessing a plurality of memory banks. The system includes a number of memory banks, a register and a controller. The register stores capacity information of each memory bank. The controller is connected to the register and memory banks and uses the capacity information to determine whether or not addresses are to be interleaved between a pair of memory banks. If the memory banks are of similar capacities, the addresses may be interleaved therebetween.

Abstract: A method for accessing data in a computer memory divided into pages. A first page is opened in response to a first address to access data therein. A second page is opened in response to a second address to access data therein. The first page is then reopened prior to receiving another address signal.

Abstract: A method for controlling access to a memory includes the step of defining a group of priority codes, each of which represents an order for granting simultaneous memory access requests. One of the group of priority codes is selectively provided to a memory controller. A request to access memory is then granted according to the selected priority code.

Abstract: A device and method for processing a plurality of asynchronous interrupt signals provided to respective primary registers. The first provided of the signals is stored in a primary register. The primary registers are then closed to subsequently provided signals. Notice is provided of receipt of the first signal, and the primary registers are read to identify the first signal. Interrupt signals received after the primary registers are closed are stored in secondary registers.

Abstract: An ink-jet print head comprises an ink drive unit formed on a first substrate and an ink reservoir unit formed on a second substrate. The ink drive unit includes a thin film piezoelectric transducer formed on one side of the substrate. The reservoir unit includes an etched cavity in the substrate for forming an ink reservoir, the cavity having an aperture in the base extending through the substrate to form an ink nozzle. The ink drive and ink reservoir units are bonded together with the piezoelectric transducer within the ink reservoir. Activating the transducer expels ink from the reservoir via the ink nozzle.

Abstract: A display device including a dot matrix type LCD display, and a digitizing tablet for interpreting movement of a stylus across the display device. Aligned with the display in a viewing direction is disposed a light transmissive panel including a structure having a plurality of light transmissive regions containing a gaseous substance, e.g. air. The regions are in register with the dot matrix generation of the LCD display. The walls of the regions may be coated with reflective material to increase their reflective properties. The structure is sealed at its open ends with sheets of transparent material to form the panel, which provides a writing surface for the stylus. Two methods of manufacturing the panel are disclosed. The display device is light in weight, low in cost and parallax errors are minimized.

Abstract: A monolithic semiconductor device includes a field effect transistor and a bipolar junction transistor with an elevated emitter structure. An elevation structure raises the BJT emitter above the plane of the base. The elevation structure increases travel distance between a heavily doped base contact region and the emitter and protects against encroachment without increasing the total surface area allocated to the BJT device. A spacer oxide separates the polysilicon base contact and the elevation structure.

Abstract: A system and method for tracking a plurality of addresses. The system comprises a plurality of registers, each register storing a current address and having an input and an output. Each input is connected to a data bus through a first multiplexer and each output is connected to an address bus through a second multiplexer. The system further comprises an adder connected between the address bus and the first multiplexer. The adder increments a current address appearing on the address bus while the address in on the bus and generates a next address.