Abstract: A data processing network having a host computer, a plurality of terminals, a cable for transmitting data between the host computer and the terminals, and a controller for controlling character data sent from the host computer to the terminals and keystroke data sent from the terminals to the host computer. Data is transmitted in a cycle of time frames, with each time frame having a plurality of time slots, one time slot being allocated to the transmission of one character from the host computer to a designated terminal. Further, each time frame includes a time slot for the transmission of a keystroke from a designated terminal to the host computer. The terminal which may transmit a keystroke to the host computer is designated in a syn/poll character generated at the beginning of each time frame by the controller.

Abstract: A device and method for generating a symmetrical clock signal. The device comprises a signal generator, buffer and differential amplifier. The signal generator generates a periodic wave signal. The buffer receives the periodic wave signal and provides a square wave clock signal. The differential amplifier receives the clock signal and a reference voltage signal and provides an error signal to the buffer.

Abstract: A control circuit and method for regulating the current flow through a series connected inductor and transistor. The circuit comprises an operational amplifier for receiving a first voltage proportional to the current flow, for receiving a variable second voltage, and for providing a control current to the transistor which keeps the transistor out of its saturation region.

Abstract: A transient immune bistable input buffer circuit. The circuit comprises a filter connected between an input and a reference voltage terminal to the circuit for reducing the sensitivity of the circuit to a voltage transient on the terminal.

Abstract: A cryogenically cooled integrated circuit apparatus is disclosed. The apparatus includes a cryogenic vessel with an integrated circuit package positioned in an opening at one end. One face of the integrated circuit is in direct contact with cryogenic fluid and a second face has a standard pin array which is connectable to a printed circuit board.

Abstract: A low current output driver for a gate array. The driver has first and second reference voltage sources, a first transistor of a first conductivity type, and a plurality of second transistors of a second conductivity type. The first transistor is connected between the first reference voltage source and the output. The second transistors are series connected between the first and second reference voltage sources. The control electrode of the first transistor is connected to a common point between two of the second transistors. At least one of the second transistors is diode connected to provide an intermediate voltage to the control electrode of the first transistor, thereby reducing the output current flow.

Abstract: An integrated circuit driver for high and low lines in a bus. The driver comprises first and second current sources connected to high and low voltage sources, respectively, and first and second transistor circuits for blocking voltage spikes higher or lower than the voltages provided by the high and low voltage sources. The first current source and the first transistor circuit are series connected between the high voltage supply and the high line, and the second current source and the second transistor circuit are series connected between the low voltage source and the low line.

Abstract: The subject invention is a power supply comprising a magnetic amplifier, filter, back-up battery, switch-over regulating circuit and error amplifier. The magnetic amplifier receives a plurality of AC pulses and controls the pulse width of the pulses. The filter converts the pulses to a DC output. The switch-over regulating circuit connects the battery to the DC output. The error amplifier monitors the DC output and provides, at its output, an error signal to the magnetic amplifier and the switch-over regulating circuit.

Abstract: An integrated circuit structure and fabrication process for creating field oxide regions having substantially no bird's beak, a relatively planar concluding surface, substantially no stress induced dislocations at the edges of the active regions, and a substantial absence of notches or grooves at the edges of the active silicon, by a selective combination of material dimensions and process operations. In one form of practicing the invention, the process utilizes a relatively thick pad oxide below the masking nitride layer, and a second, very thin, sidewall masking nitride layer. The thin sidewall masking nitride layer does not utilize an underlying pad oxide layer, but may include a thin underlying screening oxide.

Abstract: A circuit for generating clock and control signals from first and second asynchronous binary signals. The circuit generates first and second pulse signals responsive to the first and second asynchronous binary signals, a clock pulse signal responsive to the first or second pulse signal, and an identification control signal to indicate which of the two binary signals is responsible for the clock signal. The circuit is also responsive to the first and second pulse signals for generating an overlap control signal to indicate overlap in the first and second pulse signals.

Abstract: An output driver for reducing current spikes in an output comprising three transistors connected between an output node and a reference voltage terminal. The first transistor is responsive to an input data signal, the second transistor is responsive to a first feedback signal from the output, and the third transistor is responsive to a second feedback signal from the output.

Abstract: The subject invention is a method for processing a plastic packaged electronic device with soldered leads. The solder has a critical temperature which if exceeded more than once results in its oxidation. The method comprises protecting the device with a carrier, and baking the device and carrier in a low pressure environment and at a temperature sufficiently high enough to drive off moisture previously absorbed by the plastic but lower than the critical temperature of the solder.

Abstract: A method is disclosed whereby individual members of a group of members or entities may be provided, under the control of a trusted member, referred to as the parent, with respective individual secret keys for use in public key cryptography, such that the matching public key can be readily derived, and group membership authenticated. The parent initially establishes a public key (e,N) where N=P.Q is the product of two primes. In response to a request from a group member, the parent selects two further primes R,S and communicates two values dependent thereon to the requesting member, which selects two more primes T and U for use in conjunction with the received values to establish the member's secret key.

Abstract: The subject invention is an interface circuit between a requesting device and a responding device. The circuit comprises a flip-flop responsive to a request signal received from the requesting device and a handshake signal received from the responding device to generate a control signal. The circuit also comprises a gate for receiving the control and handshake signals and generating an acknowledge signal. The removal of the request signal sets the control signal to a first value which disables the gate and removal of the handshake signal resets the control signal to a second value which enables the gate.

Abstract: An entity such as a smart card includes microprocessor means, input/output means, and PROM storage means which stores a set of transformations S.sub.i (i=1, . . . , n) of a corresponding set of public factors F.sub.1 (i=1, . . . , n), where S.sub.i =F.sub.i.sup.d (mod N), d being the secret key counterpart of a public key e associated with the modulus N, which is the product of two primes. An authentication device which stores the public factors F.sub.i and the values of N and e, generates an n bit random vector v=v.sub.i which is transmitted to the card where a product Y of the values S.sub.i selected according to the 1 bits of v is computed and transmitted to the authentication device which computes X.sub.act =Y.sup.e (mod N) and also computes X.sub.ref, the product of the F.sub.i selected according to the 1 bits of v. If X.sub.act and X.sub.ref are equal, then the card is authenticated to within a certain probability. An analogous method is disclosed for certifying messages to be transmitted.

Abstract: The subject invention is a circuit and method of providing the sum of first and second n bit binary numbers having a difference of one or less. The method comprises combining the least significant bits of the numbers in a first coincidence gate to provide the least significant bit of the sum, combining the nth and (n-1)st bits of the numbers in a first logic network to provide the most significant bit of the sum, and combining solely the ith and (i-1)st bits of the numbers in an ith logic network to provide the ith bit of the sum, for all values of i where 1<i<n+1.

Abstract: A data transmission system for transferring data signals between first and second buses is disclosed. The system includes means attached to the buses for the transfer of data signals to the buses and supply means connected to the buses for precharging the buses to a first voltage level. The system also includes circuit means connecting the buses and responsive to a data signal at a second voltage level on either of said buses for transferring the signal to the other bus.

Abstract: A modular and hierarchical multiple bus computer architecture in which the master bus and slave bus are substantially identical, and communicate through a combination of an interface controller and a shared dual port RAM responsive to a shared RAM controller. Processor engine modules including a bus, a processor, an interface controller, a shared dual port RAM, and a shared RAM controller are horizontally and/or vertically integrated at multiple levels without major restructuring of the composite system control operations by having each slave processor engine module interface as a peripheral upon the bus of its master. The modularity of the architecture allows the use of standard peripherals and platform processor engines to expand memory or increase functionality without burdening the master bus processor engine. Each slave bus processor engine is fully functional as an independent processor with mastery over its own bus.

Abstract: A silicon on insulator fabrication process and structure. The fabrication process includes a reproducible sequence in which an oxide covered substrate is anisotropically etched in the presence of a mask to form trenches which extend into the substrate. Epitaxial silicon is selectively grown in the trench regions in a sucession of first materially doped and thereafter lightly doped layers. The materially doped layer extends above the plane defined by the surface of the substrate. Following a selective removal of the oxide, the materially doped epitaxial layer is exposed at its sidewalls first to an anodization and then to an oxidation ambient. This successive conversion of the materially doped epitaxial layer first to porous silicon and then silicon dioxide dielectric isolates the lightly doped epitaxial layer from the substrate.

Abstract: An inversion coupler for use in a computer system is disclosed. The computer system has a backpanel with a front side for the mounting of printed circuit boards each with a plurality of rows of connector pins. The inversion coupler mounts one of the printed circuit boards to the back side of the backpanel. The inversion coupler comprises first and second connector bodies. The first body is engageable with the pins of the board mountable to the back side and the second body is connectable to the pins of a board mountable to the front side. Each of the connector bodies has a plurality of IC pins arranged in a plurality of mutually corresponding rows. The pins in each row are connected to the pins in the corresponding row in inverse order.