Abstract: A process for forming a titanium silicide local interconnect between electrodes separated by a dielectric insulator on an integrated circuit. A first layer of titanium is formed on the insulator, and a layer of silicon is formed on the titanium. The silicon layer is masked and etched to form a silicon strip connecting the electrodes, and an overlying second layer of titanium is formed over the silicon strip. The titanium and silicon are heated to form nonsilicidized titanium over a strip of titanium silicide, and the nonsilicidized titanium is removed.

Abstract: The invention concerns an analog amplifier constructed using digital transistors. The digital transistors are those contained in a gate array, and which are used for fabrication of digital devices. The analog amplifier includes an invertor, which contains two cascode amplifiers in series. The analog amplifier also includes a differential amplifier. The invertor is contained within the feedback circuit of the differential amplifier.

Abstract: A method and system for transferring data elements from a computer main memory to a cache memory. The main and cache memories are accessible by a host processor and other bus masters connected thereto by a bus. Code data elements to be read by the host processor are predicted. The predicted code data elements are then transferred from the main memory to cache memory without delaying memory access requests for data from the other bus masters.

Abstract: A memory controller intercepts data bytes destined for a memory and selectively combines them with data bytes previously read from the memory. The controller also blocks data bytes destined for the memory corresponding to data bytes previously written to the memory. The memory controller includes an input device and an output device. An output line of the input device is connected to both the memory and an input line of the output device. Also, the memory is connected to the input line of the output device.

Abstract: The invention concerns Random-Access Memory (RAM). In many types of RAM currently available, the data on the RAM's output lines can change (or, at least, is no longer guaranteed valid) after the address applied to the RAM changes. The invention maintains the validity of the data after such address changes occur. The data is maintained valid until new data is written to the RAM.

Abstract: A method and apparatus for approximating power dissipation using a computer-assisted engineering (CAE) system. Initially, a determination is made of the capacitive load for each cell in a netlist for the CMOS circuit, preferably from cell library data sheets. In addition, the capacitive loads of the interconnects between stages are estimated. A switching rate for each cell is then calculated using one of two alternative methods. The first method assumes that the patterns of input signals are statistically independent, and thus estimates the switching rate from the structure of the cell and the switching rates of the inputs. The second method uses known information concerning the relative times when the input signals are high or low to determine the switching rate of the cell. Once the switching rate is known, the output frequency for the cell can be determined. The power dissipation for each cell is then calculated by multiplying the output frequency by the capacitive load.

Abstract: An input cell for a semiconductor chip having an I/O region proximate the edge of the chip and a core region located inside the I/O region. The input cell is located in the I/O region and includes an input pad for receiving an input signal and a multiplexer. The multiplexer receives an input signal from the pad or a boundary scan signal from the core region and selectively provides one signal or the other to the core region.

Abstract: A field effect transistor with improved electrostatic discharge (ESD) protection has a source, a channel underlying a gate electrode and a drain. The drain includes a lightly doped ballast resistor extending across the width of the drain and separating two other drain sub-regions. One drain sub-region is located between the ballast resistor and the channel, the other drain sub-region is opposite the resistor and connected to an exterior device. The ballast resistor laterally distributes current along the width of the drain during an ESD pulse, which reduces local peak current density and reduces damage.

Abstract: A three dimensional logic cube comprises a base plate having two vertically mounted backplanes attached thereto. A plurality of horizontally stacked substrates are coupled by connectors to the backplanes, with enough clearance between adjacent substrates to ensure heat dissipating air or fluid flow between the substrates. Typically, the substrates are multi-chip modules having a plurality of logic and interconnect chips attached at die mounting locations. Preferably, the logic and interconnect chips are attached to the substrate using flip TAB frames. The substrate includes a pattern interconnect for connecting together all of the chips. The logic chip is based on a standard 10K-50K gate array design with 100 micron pad spacing. The interconnect chip uses an interconnect pattern to connect the logic chips. The interconnect chip uses a lead placement identical to the logic chip, so that a single TAB frame can be used for both chips.

Abstract: An ink-jet print head comprises an ink drive unit formed on a first substrate and an ink reservoir unit formed on a second substrate. The ink drive unit includes a thin film piezoelectric transducer formed on one side of the substrate. The reservoir unit includes an etched cavity in the substrate for forming an ink reservoir, the cavity having an aperture in the base extending through the substrate to form an ink nozzle. The ink drive and ink reservoir units are bonded together with the piezoelectric transducer within the ink reservoir. Activating the transducer expels ink from the reservoir via the ink nozzle.

Abstract: A system and method for transferring a designated number d of data bytes between first and second data busses. The system includes a data buffer connected between the busses, a full counter, a partial counter, and decode logic connected to the counters. The full counter counts the total number of data bytes transferred between the buffer and the first bus. The partial counter counts data bytes transferred between the buffer and the second bus. The decode logic indicates when d data bytes have been transferred between the busses.

Abstract: An interleave lock arrangement for a computer system ensures the atomicity of a data transfer operation over a selected bus between a selected intelligent controller and a selected memory interleave, without interfering with data transfers over unselected buses between unselected intelligent controllers and unselected memory interleaves. An interleave lock signal issued by the selected intelligent controller over the selected bus is detected by and prevents only unselected intelligent controllers on the selected bus from executing bus cycles while the interleave lock signal is being asserted.

Abstract: A method of configuring a plurality of work station units, in which the units share common addresses. The units are activated one at a time with the activated unit being given configuration data corresponding to the common addresses. In this manner, an unlimited number of units of a work station can be configured with a limited number of I/O addresses.

Abstract: A method for reading data from an n-way, set associative cache. n individually addressable memory units are provided, with each of the units storing a plurality of data elements. All n of the units are concurrently addressed to transfer a data element from each of the units to a respective latch, and one of such data elements is selectively transferred from one of the latches. The units are then serially addressed in a predetermined pattern to sequentially transfer data elements out of the units.

Abstract: A typical Programmable Logic Array (PLA) provides an available logic function, or precursor, which a user modifies to obtain a desired logic function. For example, the precursor may be (A.multidot.A19 B.multidot.B+(A.multidot.A.multidot.B.multidot.B). The user obtains the desired function, such as (A.multidot.)+(A.multidot.B), by blowing fuses inside the PLA. The fuse-blowing physically blocks data signals (such as the deleted and the deleted B in the first term) from reaching an internal AND gate which performs the ".multidot." operation. However, this fuse-blowing is permanent, and irreversible. In contrast, one form of the invention does the blocking by using a NAND gate. That is, the data signal, such as the "B," is applied to one input of the NAND gate. A capacitor is connected to the other input. The user stores either a ONE or a ZERO on the capacitor. A ONE blocks the data signal (the output of the NAND cannot change). A ZERO passes the data signal (the output is the inverse of the data signal).

Abstract: A work station having a local bus connected to a CPU, and an interface chip connected between an external bus and the local bus, The buses have different operating frequencies, The interface chip includes a DMA unit and interfacing unit connected to an internal bus, The DMA unit controls data transfer between the external and local buses, The first interfacing unit includes a synchronizer for compensating for the different operating frequencies.

Abstract: A method for reading a multiple byte data element stored in both first and second memories. Selected bytes of the data element are invalidated in the first memory. Valid bytes from the first memory are combined with remaining bytes from the second memory in response to a read request.

Abstract: A work station, including a central processing unit (CPU), first, second and third integrated circuit interface chips, connected to an external bus, memory and peripheral unit, respectively, and a local bus, coupled to the CPU and chips. Each chip includes an internal bus interconnecting operating units disposed therein. Each chip is adapted to operate at the same clock frequency as the CPU, but with operational signals generated on its respective internal bus independently of the CPU. The internal bus on the first chip includes a burst mode control line for selected operating units. An operating unit obtaining access to the internal bus and activating its burst mode control line is effective to lock the internal bus for a plurality of operating cycles, during which data is transferred continuously in a burst mode over the internal bus.

Abstract: A wireless local area network (LAN) station and method for operating the same. The station has a number of antennas for communicating with a similar number of LANs, respectively. Transmissions from one antenna are blocked when the other antenna is receiving RF signals.

Abstract: A semiconductor structure comprising a polysilicon pad, a metal pad separated from the polysilicon pad by an insulator, and a metal via connecting the pads. A fuse is formed at the intersection of the polysilicon pad and via.