Patents Represented by Attorney Edel M. Young
  • Patent number: 7200235
    Abstract: Described are circuits that detect and correct for decryption key errors. In one example, a programmable logic device includes a decryption key memory with a number of decryption-key fields and, for each key field, an associated error-correction-code (ECC) field. The PLD additionally includes error-correction circuitry that receives each key and associated ECC and performs an error correction before conveying the resulting error-corrected key to a decryptor.
    Type: Grant
    Filed: May 17, 2002
    Date of Patent: April 3, 2007
    Assignee: Xilinx, Inc.
    Inventor: Stephen M. Trimberger
  • Patent number: 7117373
    Abstract: It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 3, 2006
    Assignee: XILINX, Inc.
    Inventors: Stephen M. Trimberger, Raymond C. Pang, Walter N. Sze, Jennifer Wong, Kameswara K. Rao
  • Patent number: 7117372
    Abstract: It is sometimes desirable to protect a design used in a PLD from being copied. According to the present invention, the design is encrypted, then loaded into a PLD, then decrypted, and then loaded into the configuration memory of the PLD. An attacker could relocate the design to a visible part of the PLD and learn the design. The present invention prevents design relocation by attaching address information to the encryption key or by encrypting an address where the design is to be loaded as well as encrypting the design itself. Thus, if an attacker tries to load the design into a different part of the PLD, the encrypted design will not decrypt properly.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 3, 2006
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Raymond C. Pang, Walter N. Sze, Jennifer Wong
  • Patent number: 7111273
    Abstract: A softPAL implementation and mapping method are described. The implementation utilizes both LUTs and architecture-specific logic circuits to implement softPAL functions, and selects from several implementations in order to decrease delay in function implementation. The method describes techniques for estimating p-terms in a 2-bounded sub-graph, factoring methods, mapping strategies for LUTs and dedicated logic elements, and delay optimization of critical paths.
    Type: Grant
    Filed: July 3, 2003
    Date of Patent: September 19, 2006
    Assignee: Xilinx, Inc.
    Inventors: Satish R. Ganesan, Sundararajarao Mohan, Ralph D. Wittig
  • Patent number: 7061102
    Abstract: A semiconductor flipchip package includes a central cavity area on the first major side for receiving a flipchip die therein. The package substrate is substantially made from a single material that serves as the support and stiffener and provides within the cavity floor all the connecting points for flipchip interconnection to the silicon die. The integral cavity wall serves as a stiffener member of the package and provides the required mechanical stability of the whole arrangement without the need for a separate stiffener material to be adhesively attached. The cavity walls may contain extra routing metallization to create bypass capacitors to enhance electrical performance. Optional methods to cover the silicon die enhance thermal performance of the package.
    Type: Grant
    Filed: June 11, 2001
    Date of Patent: June 13, 2006
    Assignee: Xilinx, Inc.
    Inventors: Abu K. Eghan, Lan H. Hoang
  • Patent number: 7058177
    Abstract: It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, a method for generating a bitstream for storing an encrypted design begins by generating an unencrypted bitstream including bits representing the design and bits that control loading of the design. The bits representing the design are encrypted and are combined with the bits that control loading, which are not encrypted.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: June 6, 2006
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Raymond C. Pang, Walter N. Sze
  • Patent number: 7057413
    Abstract: A method for using an FPGA to implement a crossbar switch is described. Rather than using signals routed through the general FPGA routing resources to control connectivity of the crossbar switch, the input signals only carry crossbar switch data, and the connectivity is controlled by FPGA configuration data. The crossbar switch is implemented in two parts: a template of basic and constant routing to carry input signals through the switch array in one dimension and output signals from the array in another dimension, and a connectivity part controlled by a connectivity table or algorithm to generate partial reconfiguration bitstreams that determine which of the input signals is to be connected to which of the output signals.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: June 6, 2006
    Assignee: XILINX, Inc.
    Inventors: Steven P. Young, Peter H. Alfke, Trevor J. Bauer, Colm P. Fewer
  • Patent number: 7047352
    Abstract: Structure and method for updating a system that includes a memory and a programmable logic device (PLD) retains a default PLD configuration in the memory while a new configuration is being stored in the memory, and thus protect the system from failure in case an interruption occurs while the new configuration is being stored. If a power failure interrupts the storing process, the default PLD configuration is still in the memory and can be re-loaded into the PLD and used when the system is re-started to make a further attempt at storing the new configuration. Methods are also disclosed for storing in the memory a configuration for a new PLD before the original PLD is replaced so that system hardware can be updated with minimum effort and disruption, and for dividing a directory structure into protected and unprotected regions.
    Type: Grant
    Filed: August 28, 2002
    Date of Patent: May 16, 2006
    Assignee: Xilinx, Inc.
    Inventors: Arthur H. Khu, Farshid Shokouhi
  • Patent number: 7047467
    Abstract: According to the invention, a JTAG-compliant chip having a controller that receives data provided on the TDI input pin and forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip is able to verify whether the data was correctly received by the non-JTAG chip by reading back the data and comparing to the original data. A status bit or bits are shifted out on a TDO pin and used to determine what data will be shifted in next.
    Type: Grant
    Filed: April 11, 2002
    Date of Patent: May 16, 2006
    Assignee: Xilinx, Inc.
    Inventors: Arthur H. Khu, Farshid Shokouhi, Conrad A. Theron
  • Patent number: 6984533
    Abstract: When integrated circuit dice are tested as part of a completely manufactured wafer, the individual die is tested both for proper function and for speed grade. A wafer map is formed in a computer to keep up with which dice on the wafer are good and to record the speed grade of each good die. This wafer map is then used during the step of dicing and packaging the wafer to fill existing orders by placing a die that meets a speed grade of an order into the package that has been ordered. More than one kind of order can be filled from dice in a single wafer. The method allows integrated circuit devices to be packaged to order and eliminates the need to keep an inventory of packaged dice.
    Type: Grant
    Filed: October 9, 2001
    Date of Patent: January 10, 2006
    Assignee: Xilinx, Inc.
    Inventors: Ramon R. Regos, Alelie T. Funcell
  • Patent number: 6981153
    Abstract: It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, the design may be encrypted as it is read into the PLD and decrypted within the PLD before being loaded into configuration memory cells for configuring the PLD. According to the invention, in such a device, a method is provided to prevent the design from being read back from the PLD in its decrypted state if it had been encrypted when loaded into the PLD.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: December 27, 2005
    Assignee: Xilinx, Inc.
    Inventors: Raymond C. Pang, Walter N. Sze, John M. Thendean, Stephen M. Trimberger, Jennifer Wong
  • Patent number: 6965675
    Abstract: It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being written into the PLD. It is desirable that decryption keys be stored within the PLD, and that they be loaded conveniently before a board including the PLD is sold. The invention allows the PLD to be placed into a printed circuit board and the board to be tested using a JTAG port of the PLD, and then allows the decryption keys to be loaded into a key memory using the JTAG port. Loading of the keys can be performed without also loading of a design into the PLD. Loading may be performed without the use of a device programmer.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: November 15, 2005
    Assignee: Xilinx, Inc.
    Inventors: Stephen M. Trimberger, Raymond C. Pang, John M. Thendean
  • Patent number: 6957340
    Abstract: It is sometimes desirable to protect a design used in a PLD from being copied. If the design is stored in a different device from the PLD and read into the PLD through a bitstream, an unencrypted bitstream could be observed and copied as it is being loaded. According to the invention, a bitstream for configuring a PLD with an encrypted design includes unencrypted words for controlling loading of the configuration bitstream and encrypted words that actually specify the design.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: October 18, 2005
    Assignee: Xilinx, Inc.
    Inventors: Raymond C. Pang, Stephen M. Trimberger, Jennifer Wong
  • Patent number: 6931543
    Abstract: To prevent copying of a design implemented in a programmable logic device (PLD), the PLD itself stores a decryption key or keys loaded by the designer, and includes a decryptor for decrypting an encrypted configuration bitstream as it is loaded into the PLD. The PLD also includes logic for reading header information that indicates whether the bitstream is encrypted, and can accept both encrypted and unencrypted bitstreams. The encryption keys may be stored in non-volatile memory or backed up with a battery so that they are retained when power is removed.
    Type: Grant
    Filed: November 28, 2000
    Date of Patent: August 16, 2005
    Assignee: Xilinx, Inc.
    Inventors: Raymond C. Pang, Walter N. Sze, Jennifer Wong, Stephen M. Trimberger, John M. Thendean, Kameswara K. Rao
  • Patent number: 6925583
    Abstract: According to the invention, a JTAG-compliant chip is further provided with a controller that receives data provided on the TDI input pin, forms parallel address and data instructions and passes the data through IO pins to the non-JTAG chip without requiring the data to go through the boundary scan register chain of the JTAG-compliant chip. This controller is used to program, erase, and read the other chip. For a non-JTAG flash memory device, the controller in the JTAG-compliant chip generates the necessary programming signal sequences, and applies them to the non-JTAG chip without going through the JTAG boundary scan circuitry.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: August 2, 2005
    Assignee: Xilinx, Inc.
    Inventors: Arthur H. Khu, Conrad A. Theron, Farshid Shokouhi, Pushpasheel Tawade
  • Patent number: 6904397
    Abstract: A system and method for developing a reusable electronic circuit design module are presented in various embodiments. In one embodiment, the functional design elements comprising a design module are entered into a database along with documentation elements that describe the design elements. The functional design elements are linked with selected ones of the documentation elements in the database. A testbench is simulated with the design module, and the generated results are stored in a database and linked with the functional design elements. By linking the simulation results, documentation, and design elements, the characteristics of the design module are easily ascertained by a designer who is reusing the design module.
    Type: Grant
    Filed: February 22, 2000
    Date of Patent: June 7, 2005
    Assignee: Xilinx, Inc.
    Inventors: Carol A. Fields, Anthony D. Williams
  • Patent number: 6864727
    Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.
    Type: Grant
    Filed: January 10, 2003
    Date of Patent: March 8, 2005
    Assignee: Xilinx, Inc.
    Inventors: Jack Siu Cheung Lo, Shankar Lakkapragada, Shi-dong Zhou
  • Patent number: 6838918
    Abstract: A frequency synthesizer for a programmable logic device includes a phase alignment circuit that is controlled by an asynchronous level-mode state machine. The state machine receives a start signal generated by the circuits that determine a concurrence cycle when reference and generated clock signals should be aligned. Then, at the concurrence cycle the state machine replaces a generated clock edge with a reference clock edge to bring the generated clock signal into hard phase alignment with the reference clock signal.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: January 4, 2005
    Assignee: Xilinx, Inc.
    Inventor: Alireza S. Kaviani
  • Patent number: 6836168
    Abstract: A line driver with programmable slew rates is disclosed. The line driver can be configured to have a slew rate based on a desired fraction of the clock period of the system clock. Specifically, the clock period of the system clock signal is equal to a clock period reference number multiplied by a base delay. A number of base delays is calculated to be equal to the desired fraction of the clock period multiplied by the clock period reference number. The slew rate of the line driver is adjusted to be equal to the number of base delays.
    Type: Grant
    Filed: October 2, 2002
    Date of Patent: December 28, 2004
    Assignee: Xilinx, Inc.
    Inventors: Austin H. Lesea, Atul V. Ghia
  • Patent number: 6822254
    Abstract: A non-volatile memory cell incorporated in an integrated circuit is disclosed. The non-volatile memory cell comprises an access transistor; a floating gate transistor coupled to the access transistor; a tunneling capacitor formed between the source of the access transistor and the gate of the second transistor; and a coupling capacitor having a first plate associated with a gate of the floating gate transistor, the first plate being formed to minimize the gate to source capacitance of the floating gate transistor. A window is also created to reduce the capacitance of the tunneling capacitor and the gate to source capacitance of the floating gate transistor. A method of manufacturing this non-volatile memory cell is also disclosed.
    Type: Grant
    Filed: April 4, 2003
    Date of Patent: November 23, 2004
    Inventor: Michael L. Lovejoy