Abstract: Described are systems and methods for quickly and accurately determining the set-up and hold-time requirements and clock-to-out delays associated with sequential logic elements on programmable logic devices. Programmable interconnect resources are configured to deliver signals to the data and clock terminals of each logic element under test. One or more variable delay circuits precisely place edges of the test signals on the elements of interest while a tester monitors the data clocked into the logic element to determine whether the logic element functions properly. This process is repeated for a number of selected delays.

Abstract: Method and apparatus are described for providing memory cells enhanced for resistance to single event upsets. In one embodiment, transistors are coupled between cross coupled inverters of a latch, thus in a small area providing both single-event-upset resistivity most of the time, and high speed during writing to the memory cell. Alternatively, inductors coupled between inverters of a latch may be used.

Abstract: A correlation circuit arrangement for de-spreading spread spectrum signals. In various embodiments, the correlation circuit arrangement includes an adder-subtractor and a shift register arrangement. The adder-subtractor adds an input sample value to or subtracts the sample value from an accumulated correlation value, responsive to an input PN code. The adder-subtractor is time-multiplexed between one or more PN code generators and correlation values are accumulated in the shift register arrangement. In another embodiment, transmission path delay can be analyzed by using the shift register arrangement to store correlation values that result from delaying the PN code across multiple chip periods.

Abstract: An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current.

Abstract: Described are circuits and methods for automatically measuring the program threshold voltage VTP and the erase threshold voltage VTE of EEPROM cells. The measured threshold voltages are employed to measure tunnel-oxide thickness and to determine optimal program and erase voltage levels for EEPROM circuits. One embodiment automatically sets the program and erase voltages based on the measured threshold voltages.

Abstract: A method for programming a series of in-system programmable devices that uses Boundary-Scan techniques to read device identification codes from each device of a system, and to automatically generate a board/device information file including a record for each device arranged in the order in which the devices are chained in the system. The device identification codes are then used to automatically retrieve device specifications from a central database. When no identification code is provided from the device, or the database fails to include specifications for a particular device, the user is prompted to enter minimum information or specifications necessary to carry out communications with the device. After device specifications are entered for each device, the user is prompted to enter configuration data, which is automatically matched to its associated device, and compared for consistency with the device specifications.

Abstract: An EEPROM memory cell array architecture (50) that substantially eliminates leakage current to allow for reading memory cells (20) in a memory cell array of, for example, a CPLD at lower voltages than are possible with prior art architectures, thereby facilitating development of low voltage applications. This is accomplished by associating each wordline of the memory cell array with a ground transistor (26). On one embodiment, the ground transistor (26) can be a high voltage transistor, in which case the same high voltage control signal can control both the ground transistor (26) and the memory cell=s read transistor (32). In another embodiment, the ground transistor (26) is a low voltage transistor controlled by a separate low voltage control signal.

Abstract: An improved CLB architecture, wherein the use of dedicated AND gates to generate a carry chain input signal facilitates low latency multiplication and makes efficient use of four-input function generators. In one embodiment of the invention, when multiplication using a binary addition tree algorithm is used, AND gates to implement single-bit multiplication are provided within the available function generators and duplicated in a dedicated AND gate accessible outside the corresponding function generator as a carry-chain input signal. In another embodiment, carry chain multiplexers can be selectively configured as AND or OR gates to facilitate certain arithmetic or comparison functions for the outputs of a plurality of function generators.

Abstract: A low-temperature semiconductor device test apparatus that includes a device tester having a purge box mounted thereon, a low-temperature handler system, and a load board having a IC test socket. The purge box is located between the load board and a support plate of the device tester, and between groups of compressible test pins used to pass test signals to the test socket through conductive traces formed in the load board. The purge box includes rigid outer walls defining a chamber that is located opposite to the test sockets. During low-temperature testing, dry air is pumped into the chamber through conduits formed in the walls of the purge box to prevent the condensation of moisture on conductors formed on the load board and exposed in the chamber. In addition, the purge box resists bending of the load board when semiconductor devices are pressed against the test sockets.

Abstract: A scalable physical coding sublayer (PCS) can be adjusted to provide different combinations of communication channels and data widths. The PCS can use 8B/10B encoders having a disparity input connection and at least one disparity output connection. In one embodiment, the encoder has both a synchronous and an asynchronous disparity output connection. The encoder can be coupled with additional encoders to provide an expanded width channel of 16B/20B encoding. Additional configurations are possible. In expanded operation, only one of the encoders needs to output special codes. The encoders, therefore, include a slave input connection to place the encoder in a slave mode so that a special code is replaced with an inert special code. All but one encoder in an expanded system are slave encoders. An idle input connection is also provided in the encoders to place the encoder in an idle mode where pre-defined data is output from the encoder.

Abstract: Disclosed are circuits and methods of identifying defective memory cells among rows and columns of memory cells. In one embodiment, all the memory cells in an array are programmed to conduct with a conventional read voltage applied and not to conduct with a conventional read-inhibit voltage applied. Any rows that conduct with the read-inhibit voltage applied are termed “leaky,” and are defective. Another read-inhibit voltage lower than the conventional level is selected to cause even leaky cells not to conduct. This test read-inhibit voltage is consecutively applied to each row under test. If one of the rows includes a leaky bit, that bit will conduct with the conventional read-inhibit voltage applied but will not conduct with the test read-inhibit voltage applied. The test flow therefore identifies a row as including a leaky bit when a leak is suppressed by application of the test read-inhibit voltage. A redundant row can be provided to replace a row having a leaky bit.

Abstract: A programmable capacitor in an integrated circuit (IC) comprises a conductive line located parallel to an interconnect. When a bias voltage is applied to the conductive line, a parasitic capacitance is created between the interconnect and the conductive line. By properly sizing and locating the conductive line, a desired capacitance can be coupled to the interconnect. A bias control circuit can apply or remove the bias voltage from the conductive line, thereby enabling the capacitance to be coupled or decoupled, respectively, from the interconnect. Because of its simple construction, multiple capacitive structures can be formed around a single interconnect to provide capacitive adjustment capability. By changing the number of conductive lines to which the bias voltage is applied, the total capacitance provided by the multiple capacitive structures can be varied. A feedback loop can be incorporated to provide adjustment during IC operation.

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract: A method for testing packaged integrated circuits (ICs) having bent or broken leads. A lower portion of each lead is cut to leave a stub located close to the package body of the damaged IC. The damaged IC is then mounted onto a probe card having upward-facing probes that contact the lead stubs. Test signals are then transmitted between an IC tester and the damaged IC through the probe card.

Abstract: A memory cell comprises a multilayer gate heating structure formed over a channel region between source and drain regions. The multilayer gate heating structure comprises polysilicon and metal silicide layers stacked over a similarly shaped gate oxide. When a programming voltage is applied across the metal silicide layer, there is intense localized heating. The heating causes segregation of the channel dopant atoms towards the source and drain regions, lowering the threshold voltage of the device. The heating causes carrier activation in the polysilicon layer and dopant penetration through the oxide layer into the channel region, thereby increasing the threshold voltage of the device.

Abstract: Method and system for testing circuitry of a programmable logic device (PLD). A host data processing arrangement is configured with a run-time reconfiguration programming interface, and a run-time reconfiguration test program that invokes methods of the interface executes on the host arrangement. In response to a method of the programming interface invoked from the test program, the PLD is configured with a first configuration bitstream. State data are then read back from the PLD in response to a method of the programming interface invoked from the test program. The test program also identifies differences between the state data and expected-results data.

Abstract: A configuration memory array for a programmable logic device includes an array of configuration memory cells arranged in rows and columns. Initially, each of the configuration memory cells is reset to a reset state. Each row of configuration memory cells is coupled to a corresponding data line and data line driver. During configuration, each data line driver drives a configuration data value having a first state or a second state onto the corresponding data line. A configuration data value having the first state has a polarity that tends to flip the reset state of a configuration memory cell. A repeater cell is connected to an intermediate location of each data line. Each repeater cell improves the drive of configuration data values having the first state.

Abstract: A method for determining contact resistance between an automated test equipment (ATE) system and a device under test (DUT). The DUT is configured to drive a known voltage to a pin. The ATE system is then controlled to force a first test current into the DUT at that pin. A board precision measurement unit (BPMU) of the ATE system then measures the voltage VM+ required to force the first test current. The ATE system is then controlled to force a second test current to flow out of the DUT at the same pin. The ATE system controls the second test current to have the same magnitude (but opposite direction) as the first test current. The BPMU then measures the voltage VM− required to force the second test current. The contact resistance is then determined in response to the measured voltages VM+ and VM−, and the magnitude of the test current.

Abstract: A BGA-type capacitor structure including a conventional chip capacitor mounted on the upper surface of an inexpensive substrate, and having solder balls mounted on a lower surface of the substrate. Lands that are required to mount the chip capacitor are formed on the substrate, which is offset from the surface of a PCB by the solder balls. The substrate can be a thin sheet of polyimide tape that is etched or perforated to provide holes through which the solder balls contact the lands used to mount the chip capacitor. An assembly incorporating the BGA capacitor structure includes a PCB having an array of metal vias extending between opposing upper and lower surfaces, a BGA IC mounted on the upper surface and soldered to first ends of the metal vias. The capacitor structures are soldered to contact pads formed on the lower surface of the PCB.

Abstract: A chemical mixture of liquid crystal and a substance that lowers the clear/opaque transition temperature of the liquid crystal, thins the liquid crystal, and makes the liquid crystal more sensitive to heat generated in the lower layers of an integrated circuit chip during IC hot spot testing. The substance can be a solvent or a diluent comprising a ketone or an alcohol.