Abstract: A ramp-up circuit on an integrated circuit receives a relatively high program (erase) voltage for changing the program state of a memory cell. The ramp-up circuit gradually raises the program (erase) voltage to prevent damage to the memory cell. The ramp-up circuit includes a pass gate and associated control circuitry that provides a controlled, ramped-up version of the program (erase) voltage to the memory cell without raising internal circuit nodes above the program (erase) voltage.

Abstract: An FPGA is described using optical waveguides for routing signals through the FPGA. The routing is controlled electrically. Either coupling waveguides or resonant disks can be used for routing the optical signals. Lookup tables convert optical input signals to electrical signals for selecting values in the lookup table.

Abstract: A bit-serial multiplier and an infinite impulse response filter implemented therewith, both implemented on an FPGA, are described in various embodiments. The bit-serial multiplier includes function generators configured as a multiplicand memory, a multiplier memory, a product memory, a bit-serial multiplier, and a bit-serial adder. The function generators are arranged to perform bit-serial multiplication of values in the multiplier and multiplicand memories.

Abstract: Described are methods of adapting FIB techniques to copper metallization, and to structures that result from the application of such techniques. A method in accordance with the invention can be used to sever copper traces without damaging adjacent material or creating conductive bridges to adjacent traces. Semiconductor devices that employ copper traces typically include a protective passivation layer that protects the copper. This passivation layer is removed to render the copper traces visible to an FIB operator. The copper surface is then oxidized, as by heating the device in air, to form a copper-oxide layer on the exposed copper. With the copper-oxide layer in place, an FIB is used to mill through the copper-oxide and copper layers of a selected copper trace to sever the trace. The copper-oxide layer protects copper surfaces away from the mill site from reactive chemicals used during the milling process. In one embodiment, a copper-oxide layer of at least 40 nanometers thick affords adequate protection.

Abstract: One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share routing resources of the multi-function tile. The RAM includes first and second input ports coupled to first and second input data buses, respectively, and includes first and second output ports coupled to first and second output data buses, respectively. The multiplier includes first and second operand ports coupled to receive operands from the first and second input data buses, and in response thereto provides a product. In one embodiment, the most significant bits (MSBs) of the product are selectively provided to the first output data bus using bus multiplexer logic, and the least significant bits (LSBs) of the product are selectively provided to the second output data bus using bus multiplexer logic.

Abstract: Described are programmable logic systems and methods in which programmable logic devices receive configuration data. In some embodiments, one or more input/output blocks of a programmable logic device are adapted to store a value identifying a remote memory space as a source of reconfiguration data. In other embodiments, external memory spaces for storing configuration data are adapted to store the value.

Abstract: A reticle and pellicle that are modified to prevent ESD damage to the masking material between portions of the lithographic mask pattern on the reticle during an integrated circuit fabrication process. The modification involves providing conducting lines on the glass side of the reticle and on the surface of the pellicle to balance any buildup of electrostatic charges on those devices, thereby reducing or eliminating the induction of opposite charges onto adjacent mask pattern features on the reticle and preventing the melting and bridging of those mask pattern features and the defects caused by such melting or bridging. The conductive metal lines may have a smaller width than the smallest resolution value of the reduction lens used in the mask pattern transfer process, and may also be located outside of the focal plane of the reduction lens to avoid transfer of the images of the conductive lines onto the target semiconductor substrate during the mask pattern transfer process.

Abstract: A method and apparatus are disclosed for reducing the likelihood of unintentionally or irreversibly activating one or more of a programmable logic device's output elements after a programming interruption. Output disable and enable bits are moved to near the beginning and end, respectively, of a programming bitstream, thereby maximizing the amount of time the device outputs are in high impedance mode during programming, and minimizing the risk of unintentionally driving the device outputs.

Abstract: A reticle (mask) that is modified to prevent bridging of the masking material (e.g., chrome) between long mask lines of a lithographic mask pattern during an integrated circuit fabrication process. A dummy mask pattern is provided on the reticle adjacent to long mask lines that causes the large charge collected on the long mask line to be distributed along its length, thereby minimizing voltage potentials across a gap separating the long mask line from an adjacent mask line.

Abstract: A method and assembly for testing multiple IC packages for solder joint fractures that occur in response to thermal cycling. A test PCB is fabricated with contact pads arranged to match a BGA IC package footprint, wherein pairs of the contact pads are linked by conductive traces (lines) to form a lower portion of a daisy chain. The BGA IC package is modified to link associated pairs of solder balls, e.g., using wire bonding to form an upper portion of the daisy chain. Mounting the BGA IC package on the test PCB completes the daisy chain. By alternating between the test PCB contact pads that are linked by conductive traces and the solder balls that are linked by wire bonding, the daisy chain provides a conductive path that passes through all solder balls of the BGA IC package.

Abstract: An electrical alignment test structure enables monitoring and measuring misalignment between layers (or associated masks) of an IC. The alignment test structure comprises a target region and an alignment feature in different layers. The target region and the alignment feature may be formed in diffusion and polysilicon layers, respectively or in well and diffusion layers, respectively. In both embodiments, the alignment feature controls the size of a conductive channel in the target region. Misalignment can be checked by comparing channel resistance with a baseline (no misalignment) resistance. In another embodiment, the target region and alignment feature are formed in the diffusion and polysilicon layers, respectively, wherein the alignment feature controls the relative widths of the source and drain regions. Misalignment can be checked by comparing current flow with a baseline current.

Abstract: A low pass filter (LPF) is provided that smoothes and significantly slows any change in its input voltage. The capacitance of the LPF is provided by an NMOS transistor having its source and drain tied to ground. The resistance of the LPF is provided by a plurality of series-connected PMOS transistors. The gates of the PMOS transistors are coupled to ground and therefore these transistors are conducting. The PMOS transistors are fabricated in a floating well. Therefore, the LPF eliminates any capacitive coupling between a voltage supply and the well. Thus, any variation in the supply voltage fails to affect adversely the functioning of the PMOS transistors. Thus, the LPF of the present invention can advantageously smooth and significantly slow any change in its input voltage. In one embodiment, the input voltage is a reference voltage.

Abstract: An FPGA interface device includes a microcontroller having a parallel port, a serial memory having an output port, and an on-board FPGA having a serial port coupled to the output port of the serial PROM and having a parallel port coupled to the parallel port of the microcontroller. The configuration design for the FPGA interface device's on-board FPGA and the firmware code for the interface device's microcontroller are stored in the serial memory. Upon power-up, the on-board FPGA reads the configuration design from the serial memory, and then configures itself accordingly. After properly configured, the on-board FPGA serially reads the microcontroller firmware code from the serial memory, parallelizes the firmware code, and thereafter enables the microcontroller to access the resulting parallel firmware code.

Abstract: A system and method utilize bitmaps for verifying configuration of a programmable logic device (PLD). A configuration bitstream containing configuration commands and data is converted to a configuration bitmap. The configuration bitstream is downloaded to PLD, thus programming the PLD. Readback commands and data read back from the PLD are used to generate a readback bitstream. The readback bitstream is then converted to a readback bitmap. Bits at corresponding cell locations in the readback bitmap and the configuration bitmap are compared. An error signal is output if the bits are different. In one embodiment, a mask bitmap is generated to indicate which cell locations are non-configuration memory cells and thus need not be compared.

Abstract: A negative voltage detector including a resistor divider circuit is used to translate a negative voltage into a standard CMOS logic low or logic high value. The small area consumed by the negative voltage divider allows multiple device placement within a logic device without the consumption of much area on the logic device. Additionally, the multiple devices placed may detect different negative voltage thresholds with a simple tuning of device components.

Abstract: Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Abstract: A phase-locked loop (PLL) having a wide range of oscillator output frequencies and a wide range of loop divider values is realizable in integrated form because the total capacitance of its loop filter is small. The PLL includes a first phase detector, a second phase detector, a programmable tapped-delay-line oscillator, a divide-by-M loop divider, and a programmable on-chip loop filter. The programmable filter is programmed to realize one of many loop filters. In a first step, oscillator output is fed back via the loop divider to the first phase detector. Oscillator frequency is decremented by changing tap selection inside the oscillator until the first phase detector determines that the frequency of the signal fed back via the loop divider (divide-by-M) is smaller than the frequency of an input signal. The tap control at which this frequency lock condition occurred, along with value M, is then used to determine which of the many loop filters will be used in a phase lock step.

Abstract: An interface apparatus including a nesting member having a central test area, a positioning member surrounding the test area, and several removable adapters held by the positioning member to expose a selected portion of the test area. Each removable adapter includes a central opening that is sized to receive a corresponding ball grid array integrated circuits (BGA IC). During a first test procedure, a relatively small BGA IC is inserted through the relatively small central opening of a corresponding first adapter. The first adapter is then removed and replaced with a second adapter having a relatively large central opening. A second test procedure is then performed by inserting a relatively large BGA IC through the relatively large central opening formed in the second adapter.

Abstract: A method for generating a circuit design using specified input characteristics and desired output characteristics. An algorithm is used to generate candidate circuits from the desired circuit characteristics. The candidate circuit is tested with a stimulating test apparatus to provide actual output characteristics in response to the specified input characteristics. If the actual and desired output characteristics do not match, the candidate circuit is modified and re-tested. The design process may be automated or manual.

Abstract: A system and method for evolving configuration bitstreams for a programmable logic device are disclosed. A plurality of data structures having respective sets of data are established. From the sets of data, respective configuration bitstreams are generated, wherein the sets of data are mapped to positions in the bitstreams. The configuration bitstreams are then evaluated for relative suitability to meet predetermined criteria when deployed on a programmable logic device. From the relative suitability of the configuration bitstreams, next-generation data for the data structures are generated using a genetic algorithm applied to sets of data. In the various embodiments, the configuration bitstreams eliminate resource contentions, selectively eliminate asynchronous behavior, include built-in test circuits, and are relocatable. Multiple populations of configuration bitstreams can evolve in parallel over a network.