Abstract: A method and apparatus for implementing fast sum-of-products logic in an FPGA is disclosed. The method includes literal-sharing decomposition of the sum-of-products logic to reduce the number of configurable logic block (CLB) slices required to implement wide fan-in logic functions on an FPGA. The decomposition is performed by combining product terms having similar literal patterns. The apparatus includes a CLB including a plurality of slices and a second-level logic (separate from the slices) circuit to combine the outputs of the slices. Typically, the second-level logic is an OR gate or its equivalent that implements the sum portion of the sum-of-products expression. Alternatively, a combining gate may be included within the slice to combine the output of the slice to output of another slice preceding the first slice. In this case the combing gates of each of the slices are connected in series to sum the result of the product operation of a given slice with the product operations from preceding slices.

Abstract: A clock routing circuit is coupled to receive a primary clock signal, a secondary clock signal, and a select signal, all of which may be asynchronous with respect to one another. When the select signal is in a first state, the clock routing circuit passes the primary clock signal as an output clock signal. At time TA, the select signal transitions to a second state, thereby indicating that the secondary clock signal should be routed as the output clock signal. The first clock signal is prevented from being routed as the output clock signal at time TB, wherein time TB is the first time that the first clock signal has a predetermined logic state after time TA. The output clock signal is held at the predetermined logic state at time TB. The second clock signal is then routed as the output clock signal the first time that the second clock signal transitions to the predetermined logic state after time TB.

Abstract: A circuit measures the signal propagation delay through a selected test circuit. The test circuit is provided with a feedback path so that the test circuit and feedback path together form a free-running oscillator. The oscillator then automatically provides its own test signal that includes alternating rising and falling signal transitions on the test-circuit input node. A phase discriminator samples the output of the oscillator and accumulates data representing the signal propagation delay of either rising or falling signal transitions propagating through the test circuit. The worst-case delay associated with the test circuit can then be expressed as the longer of the two. Knowing the precise worst-case delay allows IC designers to minimize the guard band and consequently guarantee higher speed performance.

Abstract: Described are mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit. Each structure includes one or more MOS transistors, each of which exhibits a threshold voltage that varies with misalignment in one dimension. The test structures are configured in mirrored pairs, so that misalignment in one direction oppositely affects the threshold voltages of the paired structures. The threshold voltages of the paired structures can therefore be compared to determine the extent and direction of misalignment. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between active implants and the windows in which active regions are formed.

Abstract: In accordance with the present invention, an FPGA input/output buffer including a tristate enable register is provided. A bus line provides the FPGA output through a tristate buffer to the pad or pin. A register controls the state of the tristate buffer. A register for providing an input signal from the pad or pin may also be provided. By placing an address on address lines controlling the register clocks, any selected one of the input/output buffers can be accessed. In one embodiment, separate addresses are provided for loading a tristate control value into the output control register and for loading data into the input register.

Abstract: A circuit arrangement and method for performing the 2-D DCT. An input permutation processor reorders input samples, constructing a logical matrix of input samples. A plurality of 1-D DCT processors are arranged to receive the reordered data and apply the 1-D DCT along extended diagonals of the matrix. The output polynomials from the 1-D DCT processors are provided to a polynomial transform processor, and the output data from the polynomial transform processor are reordered, by an output permutation processor. The 1-D DCT processors and polynomial transform are multiplier free, thereby minimizing usage of FPGA resources in an FPGA implementation.

Abstract: An integrated clock doubler and polarity control circuit are described. The circuit provides high speed response between an input signal and an output signal, achieving clock doubling by passing the input signal through a delay circuit and using the output of the delay circuit to select between two paths for inverting or not inverting the input signal to produce the output signal. In one embodiment, the inverting path is a CMOS inverter with input terminal receiving the input signal, output terminal providing the output signal, and power terminals controlled by the delay circuit.

Abstract: A circuit measures a signal propagation delay through a series of memory cells on a programmable logic device. In one embodiment, a number of RAM cells are configured in series. Each RAM cell is initialized to store a logic zero. The first RAM cell is then clocked so that the output of the RAM cell rises to a logic one. The resulting rising edge from the output of the RAM cell then clocks the second RAM cell, which in turn clocks the next RAM cell in the series. The time required for a rising edge to traverse the entire sequence of latches is the cumulative time required for the output of each RAM cell to change in response to a clock edge. Consequently, the delay through the series of RAM cells provides a measure of the time required for one of the RAM cells to store data in response to a clock edge.

Abstract: The present invention provides a tunable circuit for quickly optimizing an electrical field generated by the F-N tunneling operation. To optimize this electrical field, the charging of the positive charge pump is begun after the charging of the negative charge pump. The tunable circuit of the present invention provides a means to detect the optimal negative voltage at which pumping of the positive voltage should begin. The tunable circuit includes a resistor chain coupled between a first reference voltage and a negative voltage from a negative charge pump. When charging of the negative charge pump begins, a comparator compares the voltage at a node within the resistor chain to a second reference voltage. In accordance with the present invention, the node voltage within the resistor chain is equal to the second reference voltage when the negative voltage is equal to the voltage to be detected.

Abstract: A fast, space-efficient lookup table (LUT) for programmable logic devices (PLDs) in which the write decoder, read decoder and memory block of the LUT are modified to improve performance while providing a highly efficient layout. Both the write decoder and the read decoder are controlled by LUT input signals, and data signals are transmitted directly to each memory circuit of the memory block (i.e., without passing through the write decoder). The write decoder includes NOR gates that generate select signals used to address individual memory circuits during write operations. For dynamic latching during reading or shifting, each memory circuit includes an inverter circuit connected between the memory cell and the output terminal of the memory circuit. The read decoder includes a multiplexing circuit made up of a series of 2-to-1 multiplexers that are directly controlled by the input signals received from the interconnect resources of the PLD.

Abstract: The supply voltage to which a delay circuit's buffer stages are coupled is adjusted in response to changes in temperature according to a predetermined relationship to maintain a substantially constant buffer stage gate delay over temperature variations. Decreasing gate delays resulting from decreases in temperature are offset by decreasing the supply voltage, which in turn increases gate delays. Conversely, increasing gate delays resulting from increases in temperature are offset by increasing the supply voltage, which in turn decreases gate delays. In some embodiments, a control circuit is connected to the reference voltage circuit that supplies VCC to the delay circuit, and adjusts VCC in response to temperature to maintain substantially constant gate delay over temperature. In one embodiment, the control circuit includes a microprocessor and a look-up table containing desired supply voltage versus temperature mappings.

Abstract: A method and system for simulation of a communications bus. A simulation arrangement is configured with a behavioral agent and an application agent coupled to the bus. Bus commands are selectively loaded in the behavioral and application agent in accordance with a desired simulation sequence. The behavioral agent is configurable with phase behavior instructions that specify assertion and deassertion times for selected signals by the behavioral agent. Compliant and non-compliant bus behavior can be simulated with the phase behavior instructions.

Abstract: A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.

Abstract: A test configuration for a programmable logic device (PLD) measures and stores the relative signal-propagation delays of a pair of signal paths extending into the PLD from PLD input pins. The PLD is configured to instantiate a ring oscillator that selectively includes either signal path in the ring. The oscillator exhibits a first oscillation period when the oscillator includes the first signal path, and exhibits a second oscillation period when the oscillator includes the second signal path. The difference between the first and second periods provides a measure of the difference between the signal propagation delays of the two paths of interest.

Abstract: A sense amplifier (10) is disclosed comprising: a connecting node (12) connectable to a plurality of logic cells (13) for reading the logic states thereof; at least one output (16, 18, 20); circuitry (14) for transferring the read logic states from the connecting node (12) to the at least one output; and a circuit (50) dynamically operative to limit the voltage at the connecting node (12) substantially to a predetermined voltage. In one embodiment, the circuit (50) includes a pass transistor (46) coupled between the connecting node (12) and the transferring circuit (14) and operative to conduct the logic states read from the logic cells to the transferring circuit; and a capacitive divider circuit (54, 56) coupled to a voltage source (Vdd) for producing at a node (52) thereof the predetermined voltage as a fraction of the voltage of the source, the node (52) being coupled to the pass transistor (46) to limit the voltage at the connecting node (12) substantially to the predetermined voltage.

Abstract: A field programmable gate array (FPGA) includes a first non-volatile memory cell and a second non-volatile memory cell. Each of the two non-volatile memory cells is capable of storing at least one bit of information. The second non-volatile memory cell provides redundant storage of the information stored in the first non-volatile memory cell. A read circuit is coupled to the first non-volatile memory cell and the second non-volatile memory cell. The read circuit simultaneously reads the information stored in the first and second non-volatile memory cells, The read circuit reads the information stored in the first non-volatile memory cell even if the second non-volatile memory cell is defective or is not programmed properly. The FPGA may include a third non-volatile memory cell coupled to the read circuit, which provides redundant storage of the information stored in the first non-volatile memory cell.

Abstract: Mask-alignment detection structures that measure both the direction and extent of misalignment between layers of an integrated circuit using resistive elements for which resistance varies with misalignment in one dimension. Measurements in accordance with the invention are relatively insensitive to process variations, and the structures using to take these measurements can be formed along with other features on an integrated circuit using standard processes. One embodiment of the invention may be used to measure misalignment between two conductive layers. Other embodiments measure misalignment between diffusion regions and conductors and between diffusion regions and windows through which other diffusion regions are to be formed. A circuit in accordance with one embodiment includes row and column decoders for independently selecting mask-alignment detection structures to reduce the number of test terminals required to implement the detection structures.

Abstract: A bit-serial multiplier and an infinite impulse response filter implemented therewith, both implemented on an FPGA, are described in various embodiments. The bit-serial multiplier includes function generators configured as a multiplicand memory, a multiplier memory, a product memory, a bit-serial multiplier, and a bit-serial adder. The function generators are arranged to perform bit-serial multiplication of values in the multiplier and multiplicand memories.

Abstract: A structure and method for testing a failed integrated circuit device includes a ball grid array substrate with its heat sink removed to form a cavity where a failed bare die is to be placed. An adhesive tape is attached to the lower surface of the ball grid array substrate covering the cavity, and the die is placed into the cavity against the sticky side of the adhesive tape. Wire bonds are formed from necessary pads on the die to electrical conductors on the substrate and the cavity and bond wires are covered with epoxy. When the epoxy is cured, the adhesive tape is removed, thus exposing the back side of the die for visual inspection while under test.

Abstract: A method and system for demonstrating simulation of a communications bus. In various embodiments, methods and systems are described which support recording a simulation of a system having a communications bus and playback of the recorded simulation. Bus signal vectors are recorded by recorder logic during the simulation, and player logic reads the recorded signal vectors and provides the appropriate bus signals at the appropriate times during playback of the simulation.