Patents Represented by Attorney Erik R. Nordstrom

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  • Adjusting PLL/analog supply to track CPU core supply through a voltage regulator
    Patent number: 7724078
    Abstract: A processing device includes a Phase Locked Loop (PLL) system with an adjustable power supply designed to track the power supply provided to one or more of the cores in the processor device. The PLL no longer operates at a fixed voltage level that is held constant and independent from the requested core frequency or the core digital voltage, but rather the power supply to the phase locked loop is adjusted along with the main power supply to the processor core.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: May 25, 2010
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Chaodan Deng, Thomas P. Thomas
  • Scalable rename map table recovery
    Patent number: 7711932
    Abstract: Checkpoints may be used to recover from branch mispredictions using scalable rename map table recovery.
    Type: Grant
    Filed: December 2, 2003
    Date of Patent: May 4, 2010
    Assignee: Intel Corporation
    Inventors: Haitham H. Akkary, Ravi Rajwar, Srikanth T. Srinivasan
  • Equalizers and offset control
    Patent number: 7697601
    Abstract: In some embodiments, equalizer circuits with controllably variable offsets at their outputs are provided.
    Type: Grant
    Filed: November 7, 2005
    Date of Patent: April 13, 2010
    Assignee: Intel Corporation
    Inventors: Mozhgan Mansuri, Frank O'Mahony, Bryan K. Casper, James E. Jaussi
  • PLL with controllable bias level
    Patent number: 7688150
    Abstract: Embodiments disclosed herein may provide circuits having two or more different supplies to separately power analog and digital components in a circuit. In some embodiments, circuits such as PLLs may be provided with adjustable analog supplies. Other embodiments may be disclosed and/or claimed herein.
    Type: Grant
    Filed: November 29, 2006
    Date of Patent: March 30, 2010
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Ravindra B. Venigalla
  • Device selection circuit and method
    Patent number: 7688628
    Abstract: Embodiments of the invention take advantage of an unused state of an interface protocol (or specification), such as the ONFI specification, to control a selector circuit to assert one of a plurality of relatively localized device selection signals (e.g., chip enable signals).
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: March 30, 2010
    Assignee: Intel Corporation
    Inventor: Knut Grimsrud
  • Missing clock pulse detector
    Patent number: 7679404
    Abstract: A method to detect a missing a clock pulse is provided. The method begins by providing a clock signal and a delayed clock signal. The delayed clock signal is then sampled to generate a sample of the delayed clock signal. A missing clock pulse may be detected if the sample of the delayed clock signal does not equal an expected value of the delayed clock signal.
    Type: Grant
    Filed: June 23, 2006
    Date of Patent: March 16, 2010
    Assignee: Intel Corporation
    Inventor: Mark L. Neidengard
  • Power management integrated circuit
    Patent number: 7671456
    Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.
    Type: Grant
    Filed: July 3, 2007
    Date of Patent: March 2, 2010
    Assignee: Intel Corporation
    Inventors: Siva G. Narendra, James W. Tschantz, Howard A. Wilson, Donald S. Gardner, Peter Hazucha, Gerhard Schrom, Tanay Karnik, Nitin Borkar, Vivek K. De, Shekhar Y. Borkar
  • Clock synchronizer
    Patent number: 7659762
    Abstract: Disclosed herein are synchronization latch solutions.
    Type: Grant
    Filed: March 27, 2007
    Date of Patent: February 9, 2010
    Assignee: Intel Corporation
    Inventor: Mark E. Schuelein
  • Floating body memory array
    Patent number: 7652910
    Abstract: Provided herein are embodiments of layouts for applying impact ionization potentials across the channel of a selected floating body cell in an array without having to impose the potential on other unselected cells.
    Type: Grant
    Filed: June 30, 2007
    Date of Patent: January 26, 2010
    Assignee: Intel Corporation
    Inventors: Uygar E. Avci, Peter L. D. Chang, Dinesh Somasekhar
  • Logic with state retentive sleep mode
    Patent number: 7649385
    Abstract: Embodiments disclosed herein provide sleep mode solutions for retaining state information while reducing power in a logic block.
    Type: Grant
    Filed: August 7, 2006
    Date of Patent: January 19, 2010
    Assignee: Intel Corporation
    Inventors: Aurobindo Dasgupta, Mark Schuelein
  • Integrated inductor
    Patent number: 7636242
    Abstract: An inductor and multiple inductors embedded in a substrate (e.g., IC package substrate, board substrate, and/or other substrate) is provided herein.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: December 22, 2009
    Assignee: Intel Corporation
    Inventors: Peter Hazucha, Edward Burton, Trang T. Nguyen, Gerhard Schrom, Fabrice Paillet, Kaladhar Radhakrishnan, Donald S. Gardner, Sung T. Moon, Tanay Karnik
  • Mechanism for adaptively adjusting a direct current loadline in a multi-core processor
    Patent number: 7636864
    Abstract: A central processing unit (CPU) is disclosed. The CPU includes two or more processing cores and a power control unit to regulate voltage applied to the CPU based upon the number of processing cores that are active.
    Type: Grant
    Filed: May 3, 2006
    Date of Patent: December 22, 2009
    Assignee: Intel Corporation
    Inventor: Edward Burton
  • Link transmitter with reduced power consumption
    Patent number: 7609091
    Abstract: With some transmitter embodiments disclosed herein, static power consumption in low power modes may be reduced without excessively increasing latency.
    Type: Grant
    Filed: September 29, 2005
    Date of Patent: October 27, 2009
    Assignee: Intel Corporation
    Inventors: Harry Muljono, Stefan Rusu, Yanmei Tian, Mubeen Atha, David J. Ayers
  • Delay stage with controllably variable capacitive load
    Patent number: 7605668
    Abstract: Disclosed herein are embodiments of controllably variable capacitor loads that may be used with delay stages or other elements, for example, in a voltage controlled oscillator.
    Type: Grant
    Filed: December 12, 2006
    Date of Patent: October 20, 2009
    Assignee: Intel Corporation
    Inventors: Eyal Fayneh, Ernest Knoll
  • Domino circuit with disable feature
    Patent number: 7592840
    Abstract: Some embodiments provide dynamic circuits with dynamic nodes that may float during a disable mode to reduce leakage.
    Type: Grant
    Filed: November 8, 2006
    Date of Patent: September 22, 2009
    Assignee: Intel Corporation
    Inventors: Kin Yip Sit, Shahram Jamshidi
  • Transmitter compensation
    Patent number: 7590392
    Abstract: In some embodiments, a chip with a transmitter having a transmitter driver is provided. Also provided is a general compensation circuit coupled to the transmitter to generally compensate the transmitter driver and a specific compensation circuit coupled to the transmitter driver to specifically compensate the transmitter driver. Other embodiments are disclosed and claimed herein.
    Type: Grant
    Filed: October 31, 2005
    Date of Patent: September 15, 2009
    Assignee: Intel Corporation
    Inventors: Navindra Navaratnam, Aninda K. Roy
  • Monitor implementation in a multicore processor with inclusive LLC
    Patent number: 7590805
    Abstract: A method and apparatus to implement monitor primitives when a processor employs an inclusive shared last level cache. By the employing an inclusive last level cache, the processor is almost always able to complete a monitor transaction without requiring self snooping through the system interconnect.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: September 15, 2009
    Assignee: Intel Corporation
    Inventors: Krishnakanth V. Sistla, Bryan L. Spry
  • VCO amplitude control
    Patent number: 7583151
    Abstract: Disclosed are circuits and methods to control the amplitude of a signal generated by a VCO.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: September 1, 2009
    Assignee: Intel Corporation
    Inventors: Yongping Fan, Ian Young
  • Fault free store data path for software implementation of redundant multithreading environments
    Patent number: 7581152
    Abstract: A method for a fault free store data path in a software implementation of redundant multithreading environments is described. In one embodiment, after a check is performed by a hardware/software checker, the processor still needs to ensure that the data just checked reaches protected memory without any faults. The present implementation provides sufficient redundant information along the path of a store from register read to commit, such that it may detect any single bit upset error in the path.
    Type: Grant
    Filed: December 22, 2004
    Date of Patent: August 25, 2009
    Assignee: Intel Corporation
    Inventors: Shubhendu S. Mukherjee, Robert Cohn
  • Voltage regulator
    Patent number: 7564299
    Abstract: In some embodiments, regulator circuits are provided.
    Type: Grant
    Filed: August 22, 2005
    Date of Patent: July 21, 2009
    Assignee: Intel Corporation
    Inventors: Joseph Shor, Eyal Fayneh