Abstract: For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.

Abstract: disclosed herein are embodiments of a swing compensation scheme for compensating errors in a transmitter driver.

Abstract: In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.

Abstract: A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Abstract: A computer system includes two or more subsystems. In one example, a first subsystem is executing a multimedia application using data stored in a first storage device. A copy of the data is also stored in a second storage device associated with a second subsystem. The second subsystem may be a dedicated multimedia player controller. When the first subsystem is to enter a sleep state, the second subsystem may continue to process the multimedia data stored in the second storage device. The second subsystem may also use the same audio port that the first subsystem was using before it enters the sleep state. Appropriate transition point may be determined by the second subsystem to ease audio disruption.

Abstract: Disclosed are embodiments of a phase control circuit with an analog phase controller having first and second order integration. In some embodiments, the analog control circuit generates first and second control signals and controls the first control signal based on the sign of the second control signal and controls the second control signal based on the sign of the first control signal.

Abstract: Disclosed herein are various embodiments of circuitry and methods to convert from a binary value to a BCD value.

Abstract: A method for adjusting the voltage and frequency to minimize power dissipation in a processor. The method of one embodiment comprises determining a power consumption value. The power consumption value is evaluated to obtain a new operating point. The new operating point is compared with a present operating point. A frequency setting and a voltage setting are adjusted to correspond to the new operating point if the new operating point is different from the present operating point.

Abstract: A front end for a radio frequency tuner, for example for connection to a cable distribution network, including an input connected to a signal path comprising an LNA connected via an AGC stage to a signal splitter. The input path has a bandwidth sufficiently wide to pass all of the channels in an input signal and has a substantially constant voltage standing wave ratio over the bandwidth. The splitter supplies identical signals to several filtering paths, each of which comprises a fixed filter. The paths are selectable one at a time and the filters divide the input frequency band into a plurality of contiguous or slightly overlapping sub-bands. The output of the front end is supplied to, for example, a double conversion arrangement comprising an upconverter and a downconverter with first and second IF filters.

Abstract: In some embodiments, a clock generator is provided that provides a generator clock. The clock generator comprises a first clock source to provide a first clock and a second clock source to provide a second clock whose frequency at least indirectly tracks a supply to a clock distribution network. The clock generator selectably provides as the generator clock the first clock when the second clock leads the first clock and the second clock when it lags behind the first clock. Other embodiments are claimed and disclosed herein.

Abstract: In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.

Abstract: Scanning a layer of a layout in a first direction and selecting a first rectangle in a scan order, scanning the layer of the layout in a second direction orthogonal to the first direction to find a second rectangle that intersects the first rectangle, and if the second rectangle is found, performing a union of the first and second rectangles to generate a set of non-intersecting rectangles equivalent to the first and second rectangle.

Abstract: In some embodiments, the invention provides a chip with at least one memory circuit that comprises a majority voter circuit with first and second digitally controlled variable delay elements. The first delay element is controlled by data bits that are to be written to a portion of the memory circuit. The majority voter circuit determines if the data bits are to be inverted prior to being written into the memory circuit portion.

Abstract: A computer system includes a panel that when unfolded may expose a keyboard and a stand. The stand is to support the computer system in its upright position. The keyboard may be a wireless keyboard and may be part of a keyboard tray. When the panel is unfolded, the keyboard may be slid into or out of the stand. When the keyboard is slid into the stand, the keyboard tray and the stand form the panel. When the panel is folded, a carrying handle may be used to carry the computer system from one place to another place.

Abstract: A system and method of scheduling packets in a multi-threaded, multiprocessor network architecture provides enhanced speed and performance. The architecture involves a scheduler thread that transitions between queues in response to a depletion of queues by a weighted amount, a plurality of transmit threads that deplete the queues by the size of packets transmitted and a plurality of receive threads that initialize the weights for idle queues.

Abstract: A mechanism detects multiple assertions in a bus efficiently by encoding each of N bus lines with log2(N) pairs of bit lines.

Abstract: For one disclosed embodiment, an apparatus comprises a first p-type device coupled between a cell voltage node and a storage node, an n-type device coupled between the storage node and a reference voltage node, and a second p-type device to couple the storage node to a bit line in response to a signal on a select line. At least one side of diffusion regions in a substrate to form both the first p-type device and the second p-type device are substantially aligned. Other embodiments are also disclosed.

Abstract: Disclosed herein are techniques for reducing standby power consumption due to leakage currents in memory array circuits.

Abstract: A network interface between an internal bus and an external bus architecture having one or more external buses includes an external interface engine and an internal interface. The external interface engine (EIE) is coupled to the external bus architecture, where the external interface engine communicates over the external bus architecture in accordance with one or more bus protocols. The internal interface is coupled to the external interface engine and the internal bus, where the internal interface buffers network data between the internal bus and the external bus architecture. In one embodiment, the internal interface includes an internal interface (IIE) coupled to the internal bus, where the IIE defines a plurality of queues for the network data. An intermediate memory module is coupled to the IIE and the EIE, where the intermediate memory module aggregates the network data in accordance with the plurality of queues.

Abstract: Different embodiments of a one-time-programmable antifuse cell included. In one embodiment, a circuit is provided that includes an antifuse element, a high voltage device, and a sense circuit. The antifuse element has a voltage supply terminal to be at a sense voltage during sensing/reading and a higher programming voltage during programming. The sense circuit is configured to enable programming the antifuse element during programming and to sense the state of the antifuse element during sensing. The high voltage device is coupled between the antifuse element and the sense circuit to couple the antifuse element to the sense circuit during programming and sensing and to protectively shield the sense circuit from the higher programming voltage during programming.