Abstract: A method and apparatus for improving the performance of an edge launch electrical connector. Two or more edge vias are established along an edge face of a planar circuit module, such as a single- or multi-layer PCB, integrated circuit on a ceramic or organic substrate or a ceramic or organic package, thereby providing a short path from one or more of the substrate assembly's ground planes to a ground associated with the edge launch electrical connector, reducing jitter and providing a solution with low insertion and return losses. The two edge vias may be standard vias, castellations or wires or lines deposited, printed, painted, secured or put in contact with an edge face of the planar circuit module and are arranged at each side of the signal line thereby providing additional electromagnetic shielding. Optionally, an air line may be established to increase the operational cut-off frequency and/or improve electrical performance.

Abstract: A multi-sensor system for the real-time embedded monitoring of an object senses mixed-mode object conditions. Various sensors separately provide disparate analog signals representing different measurable attributes regarding the sensed object. For example, such sensors may separately sense temperature, pressure, or other biometric value. Then, according to a specified rule set or other qualifying parameters, a digital signal is generated by a processor or controller to indicate one or more condition of the sensed object according to certain sensor input values. Additionally, such multi-sensor scheme may be coupled to a digital network or otherwise coupled thereto for simulation and/or communication applications.

Abstract: A refresh scheme for a semiconductor memory macro that comprises three-transistor dynamic random access memory (3T-DRAM) cells. Similar to an internal refresh operation, an external access command is also interpreted as a read-then-write operation. A clock cycle is partitioned as a plurality of time slots by an internal clock generator. Each time slot is assigned to execute a specific memory cell operations, whereby array idle time typically needed for performing exclusively non-array operations is no longer required. An external access and an internal refresh can be operated sequentially without degrading speed performance. An internal refresh can occur in every clock cycle period to retain the stored data. This clock cycle period is less than the time required for consecutively performing the external access and thereafter the internal refresh upon the completion of the external access.

Abstract: A process for creating a broadly tunable Distributed Bragg Reflector (DBR) with a reduced recombination rate. According to the current invention, this may be achieved by creating electron confinement regions and hole confinement regions in the waveguide of the DBR. Preferably, this is achieved by engineering the band gaps of the DBR waveguide and cladding materials. Preferably, the materials selected for use in the DBR may be lattice matched. Alternately, two or more thin electron confinement regions and two or more thin hole confinement regions may be created to take advantage of strain compensation in thinner layers thereby broadening the choices of materials appropriate for use in creating a broadly tunable DBR. Alternately, graded materials and/or graded interfaces may be created according to alternate processes according to the current invention to provide effective electron and/or hole confinement regions in various DBR designs.

Abstract: A moisture detector is presented which uses the effects of moisture on the chemistry and electrical conductivity of drywall material. Conducting probes are installed in a drywall material and the level of electric current between the probes is monitored and correlated with the concentration of moisture in the drywall material along a path between the probes.

Abstract: The invention discloses a relative structure placement of datapath of cell instances in a column structure, a row structure, or an array structure. To encourage placement of a desirable structure, pseudo cells, pseudo pins, and pseudo nets are selected to be placed at certain locations with respect to real cell instances. The end result produces a cluster of real cell instances that form a desirable structure while minimizing the length of nets. The invention further discloses a non-uniform partitioning of a density map for calculating a force update vector. The partitioning is taken over a region A to compute Riemann sum approximations of a function F over the region A. A force update vector is calculated for a given cell instance within the region A where neighboring cell instances have an exponentially larger grid size as cell instances extend further away from the given cell instance.

Abstract: A programmable and non-volatile analog signal storage structure and method are disclosed that employ two non-volatile cells which are arranged as a differential transistor pair. The non-volatile transistor at the positive (or non-inverting) terminal of the amplifier is referred to as the reference cell, while the non-volatile transistor on the negative (or inverting) input of the amplifier is referred to as the storage cell. The structure comprises a storage cell and a reference cell that produces a voltage which is independent of temperature and supply voltage variation. Additionally, the circuit structure is capable of operating at low supply voltage levels (<1.5V).

Abstract: The present I/O ports comprise (1) a layered structure comprising (a) an unpatterned superstrate having at least one layer, (b) an unpatterned substrate having at least one layer, and (c) at least one intermediate layer sandwiched between the unpatterned superstrate and the unpatterned substrate, (2) a coupling region that is within the at least one intermediate layer and that comprises an arrangement of at least one optical scattering element and (3) at least one output waveguide. The present I/O ports can be effectively used in balanced photonic circuits and unbalanced photonic circuits.

Abstract: A method and apparatus for resolving priority among a plurality of data values. The priority resolution method of the invention analyzes the data values one bit at a time, starting from the most significant bit. In one embodiment, at an initial analysis step, the method determines whether the most significant bits of the data values are asserted. If at least one of the most significant bits is asserted, the data values that have unasserted most significant bits are eliminated from consideration. If none of the most significant bits is asserted, none of the data values will be eliminated at the initial step. The same analysis steps are repeated for each successive bit until only the largest data values remain. The priority resolution method of the present invention may be used to determine the smallest data value. In that embodiment, the data values are first bit-wise inverted.

Abstract: A fingerprint recognition method includes iterative gamma correction that compensates moisture effect, feature extraction operations, directional morphological filtering that effectively links broken ridges and breaks smeared ridges, adaptive image alignment by local minutia matching, global matching by relaxed rigid transform, and statistical matching with Gaussian weighting functions.

Abstract: For use in capturing a fingerprint image, an optical fingerprint sensor. In one embodiment of the present invention, the optical fingerprint sensor includes: (1) a light source on a PCB assembly, (2) a diffuser that receives light from the light source, (3) a right angle prism that receives light from the diffuser, (4) a collimating lens that receives light from the prism, (5) a first mirror that receives light from the collimating lens, (6) a second mirror that receives light from the first mirror, (7) a third mirror that receives light from the second mirror, (8) an imaging lens that receives light from the third mirror, and (9) an image sensor on the same PCB assembly as the light source that receives light from the imaging lens.

Abstract: A patient monitor system implemented by a service provider for users via recording a patient's analytes measurements by an attenuated total reflection (ATR) infrared total spectroscopy method. The system comprises an input module that provides a non-invasive method in measuring analytes in a patient, such as a measurement of the glucose level and other blood analytes. The measurement is shared among a plurality of output devices such as computers, personal digital assistants (PDAs), cellular phones, and pagers that are stationed or held by various users, such as doctors, patients, researchers, pharmacies, labs, and health insurers. In addition, behavioral attributes are recorded and correlated with the analytes measurements to generate a profile. The profile is selectively sent to output devices based on the user profile corresponding to the output device. Also, access to the profile is monitored by a security module that encrypts the profile to prevent access by un-authorized users.

Abstract: A range match circuit is disclosed for fast compare of an incoming address by partitioning the incoming address into fields. In one embodiment, a 16-bit incoming address is divided into quarterly fields, or four segments of 4-bit addresses, for comparison with a 16-bit top end boundary that has been divided into quarterly fields and a 16-bit bottom end boundary that has been divided into quarterly fields. Consequently, the range match circuit is able to analyze the entire 16-bit address field in parallel and perform simple combinational logic to determine if the incoming address is within the boundaries described by the top edge and bottom edge of the range.

Abstract: A fiber routing tray to hold, organize, and route fiber cables from external sources to other optical modules and optical components. The fiber routing tray mechanical device comprises a fiber entry block, fiber channel slot, retention bar with fiber clamps, fiber clamping slots, curved fiber routing fence, and a fiber exit opening. A retention bar with a contoured fiber retention clamps is used to hold fiber cables in place, provide a strain relief to a fiber cable, and distribute uniform clamping force on the fiber cable preventing insertion and return losses. Curved fiber channel slots with a preferable width help route fiber cables and prevent them from overbending. In addition, these fiber channel slots control the extension and retraction distance of the fiber cables during external fiber cable assembly. A curved fiber routing fence help route fiber cables and help prevent them from over-bending and tangling inside of the fiber reel tray.

Abstract: Digital-to-analog converter architecture guarantees monotonicity and partial compensation for integral non-linearity. Two stages are separated by a unity-gain operational amplifier, wherein the first stage is a 1-bit resistor string-converter, having one end at reference high voltage, and the other end at reference low voltage, and the second stage is a multi-bit resistor string converter. The architecture relieves matching accuracy necessary for 1-bit front end. Resistor mismatch is compensated by varying buffer amplifier offset-voltage, and ensuring amplifier output is halfway between reference voltages; this improves integral non-linearity, or absolute accuracy, by the amount of mismatch present in the resistor string. Buffer amplifier at output of second stage of DAC controls INL error by varying offset voltage.

Abstract: An electronic apparatus with a high inductive reactance for differential signals per unit area and a small inductive reactance for common-mode signals relative to its inductive reactance for differential signals with predictable and scalable characteristics. This may be achieved by configuring transmission line pairs such that currents associated with the differential component of a source signal in the first and second transmission lines are aligned and currents associated with the common mode component of a source signal in the first and second transmission lines are counter-aligned. Advantageously, the current invention may be implemented using currently available technology and integrated into a variety of different devices such as broad-band and narrow-band amplifiers, high-speed logic gates, mixers, oscillators, wireless local area networks, global positioning systems and modern communication systems.

Abstract: A method and system for broadband transition between an integrated circuit (IC) package and a printed wiring board (PWB). A vertical quasi-coaxial cable structure is created connecting the transmission line inside the package to the transmission line on the PWB. The solder ball is eliminated and replaced with ad hoc layout on the bottom of the package, with mating layout on the top layer of the PWB. Complete transition from package to PWB is considered, giving particular attention not only to the impedance of the lines and the transition but also to the continuity of the current flow along the signal path.

Abstract: Integrated imaging and GPS network monitors remote object movement. Browser interface displays objects and detectors. Database stores object position movement. Cameras detect objects and generate image signal. Internet provides selectable connection between system controller and various cameras according to object positions.

Abstract: A short synchronization time modem comprising a GPS receiver for receiving a broadcasted signal comprising a high precision clock. When a first short synchronization data modem communicates with a second, a PLL in each data modem synchronizes its own local clock to the same high precision clock derived from the same received broadcasted signal. The modems connect for the first time using one of many clock recovery schemes known to the modem designers. Once they disconnect, the modems keep their clocks synchronized using a local GPS receiver and the received broadcasted signal. This prevents the local clock of the modems from drifting, which significantly reduces the time period the modems need to synchronize the next time they connect.

Abstract: An on-chip FPN calibration method and circuits scheme applying a reference voltage signal to an array of calibration pixels coupled to a sensor matrix. Two data values are read from each bit line and used to calculate an offset and a gain error for a pixel column. A reference offset and a reference gain error value are then generated by computing the average offset and the average gain error from the collected offset and gain error values of each bit line. Calibration data for each bit line then comprises an offset difference and a gain error difference, the offset difference comprising the difference between the offset value for that bit line and the reference offset, and the gain error difference comprising the gain error difference between the gain error for that bit line and the reference gain error. The calibration data for each bit line is then stored in on-chip volatile memory and is used later under normal operation to compensate for the FPN effect.