Patents Represented by Attorney Fernandez & Associate LLP
  • Patent number: 7104447
    Abstract: Parking meters detect presence of vehicles in monitored parking spaces and obtain images of license plates. A parking enforcement system communicates with the parking meters and manages use of parking spaces.
    Type: Grant
    Filed: December 15, 2003
    Date of Patent: September 12, 2006
    Inventors: Anthony Lopez, Manuel Quijano
  • Patent number: 7098815
    Abstract: A compression method and apparatus identifying candidates for compression by selectively fingerprinting shingles or overlapping subsets of an input dataset and creating a set of characteristic input fingerprints based on fingerprint value. In some cases, the characteristic fingerprints are selected based on the relative value of the fingerprints with respect to other fingerprints in the same cluster. Potential matches may be identified and confirmed by comparing the characteristic input fingerprints with fingerprints associated with a history. Advantageously, some examples according to the current invention may be applied to input data such as: data, files, bit streams, byte streams, packet streams and previously encoded, compressed and/or encrypted data.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: August 29, 2006
    Assignee: Orbital Data Corporation
    Inventors: Allen Samuels, Paul Sutter, Robert Plamondon
  • Patent number: 7095936
    Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical devices such as the core of an optical waveguide or a light scatterer will damage the devices and prevent the passage of light through those sections of the devices. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: August 22, 2006
    Assignee: Luxtera, Inc.
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
  • Patent number: 7085443
    Abstract: High speed optical modulators can be made of a lateral PN diode formed in a silicon optical waveguide, disposed on a SOI or other silicon based substrate. A PN junction is formed at the boundary of the P and N doped regions. The depletion region at the PN junction overlaps with the center of a guided optical mode propagating through the waveguide. Electrically modulating a lateral PN diode causes a phase shift in an optical wave propagating through the waveguide. Each of the doped regions can have a stepped or gradient doping profile within it or several doped sections with different doping concentrations. Forming the doped regions of a PN diode modulator with stepped or gradient doping profiles can optimize the trade off between the series resistance of the PN diode and the optical loss in the center of the waveguide due to the presence of dopants.
    Type: Grant
    Filed: August 11, 2004
    Date of Patent: August 1, 2006
    Assignee: Luxtera, Inc.
    Inventors: Lawrence C. Gunn, III, Roger Koumans, Bing Li, Guo Liang Li, Thierry J. Pinguet
  • Patent number: 7085408
    Abstract: Methods and systems for testing an image sensor system-on-chip (SOC). For testing an image sensor SOC that integrates a sensor array and an image processing component, defects are being searched separately in the sensor array and the image processing component in order to isolate possible defects of the sensor array from the possible defects of the image processing component. In so doing, the location of the defects can be pin-pointed.
    Type: Grant
    Filed: July 16, 2002
    Date of Patent: August 1, 2006
    Assignee: Magna Chip Semiconductor
    Inventor: Li Chung-Chi Jim
  • Patent number: 7082246
    Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: July 25, 2006
    Assignee: Luxtera, Inc.
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
  • Patent number: 7082247
    Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: July 25, 2006
    Assignee: Luxtera, Inc.
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier, Jeremy Witzens, Zhen-Li Ji
  • Patent number: 7082245
    Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: July 25, 2006
    Assignee: Luxtern, Inc.
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
  • Patent number: 7079742
    Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: July 18, 2006
    Assignee: Luxtera, Inc.
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
  • Patent number: 7076742
    Abstract: A treemap generation engine enables a user of a treemap generation application to design a treemap display page by providing inputs that define the format of the treemap display page, as well as inputs that define the data to be represented by the treemap display page. Based on the inputs, the treemap generation application generates treemap display data that can be processed by a browser application to draw a treemap display page on a computer.
    Type: Grant
    Filed: August 13, 2002
    Date of Patent: July 11, 2006
    Assignee: The Hive Group
    Inventors: Matthew Thorn, Donald Hoffman, Daniel Perkel
  • Patent number: 7072998
    Abstract: Method and system for generating an optimized full signal in a FIFO device. In one embodiment of the present invention, the optimized full signal control circuit checks the storage capacity of the FIFO memory by aggregating the number of occupied word entries and the number of occupied pipelines.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: July 4, 2006
    Assignee: Via Technologies, Inc.
    Inventor: Hsilin Huang
  • Patent number: 7072556
    Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: July 4, 2006
    Assignee: Luxtera, Inc.
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier, Bing Li
  • Patent number: 7071981
    Abstract: A cost-effective image capture apparatus is presented which achieves high shutter speed without blurring the captured image or introducing noise. The apparatus uses standard 4T pixels to store exposure information on the pixel itself and employs a near simultaneous reset mechanism to reset the pixels, thereby achieving high-speed image capture without increasing the per pixel die area for extra storage or incurring unwanted current spikes and noise due to simultaneous resets.
    Type: Grant
    Filed: July 1, 2002
    Date of Patent: July 4, 2006
    Assignee: MagnaChip Semiconductor, Ltd.
    Inventor: Bor-Yuan Chester Hwang
  • Patent number: 7068887
    Abstract: A polarization splitting grating coupler (PSGC) connects an optical signal from an optical element, such as a fiber, to an optoelectronic integrated circuit. The PSGC separates a received optical signal into two orthogonal polarizations and directs the two polarizations to separate waveguides on an integrated circuit. Each of the two separated polarizations can then be processed, as needed for a particular application, by the integrated circuit. A PSGC can also operate in the reverse direction, and couple two optical signals from an integrated circuit to two respective orthogonal polarizations of one optical output signal sent off chip to an optical fiber.
    Type: Grant
    Filed: October 26, 2005
    Date of Patent: June 27, 2006
    Assignee: Luxtera, Inc.
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier, Jeremy Witzens
  • Patent number: 7061380
    Abstract: A single integrated circuit provides communication, sensing and recording of one or more conditions critical to the entity to which it is attached. The chip is part of a larger module comprising a visual indicator, such as an LED, and a power source such as a battery. The sensor may be a temperature sensor whose output is stored in a non-volatile memory section of the chip on some periodic basis. A product identifier is stored on the chip; a method for product recall or location is described.
    Type: Grant
    Filed: November 5, 2003
    Date of Patent: June 13, 2006
    Assignee: Alta Analog, Inc.
    Inventors: Richard V. Orlando, Trevor A. Blyth
  • Patent number: 7058273
    Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: June 6, 2006
    Assignee: Luxtera, Inc.
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
  • Patent number: 7054534
    Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: May 30, 2006
    Assignee: Luxtera, Inc
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
  • Patent number: 7054533
    Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical elements such as the core of an optical waveguide or a light scatterer will damage the elements and prevent the passage of light through those sections of the elements. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    Type: Grant
    Filed: July 15, 2005
    Date of Patent: May 30, 2006
    Assignee: Luxtera, Inc
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier
  • Patent number: 7046895
    Abstract: Optoelectronic devices of the present invention include several embodiments of an electronically active optical waveguide made of a strip loaded waveguide with a lateral, self-aligned diode fabricated in a layer of silicon. A voltage applied across the diode changes the free carrier density in a portion of the active waveguide, which can change the refractive index in that portion of the waveguide. Changing the refractive index can cause a phase shift of an optical signal propagating down the waveguide and this effect can be used to control the optical signal. Changing the free carrier density can also change the amount of optical attenuation in a section of an active waveguide. Optoelectronic devices such as: modulators, attenuators, switches, beam diverters, tunable filters and other devices can be fabricated on a standard SOI substrate (silicon on insulator), which is typically used in the fabrication of CMOS integrated circuits.
    Type: Grant
    Filed: November 8, 2005
    Date of Patent: May 16, 2006
    Assignee: Luxtera, Inc.
    Inventors: Lawrence C. Gunn, III, Bing Li, Thierry J. Pinguet, David Press, Maxime Jean Rattier
  • Patent number: 7046894
    Abstract: In a standard CMOS process, a layer of metallic salicide can be deposited on those selected portions of an integrated circuit, where it is desired to have metallic contacts for electronic components, such as transistors. The deposition of a salicide into optical devices such as the core of an optical waveguide or a light scatterer will damage the devices and prevent the passage of light through those sections of the devices. Prior to the deposition of the salicide, a salicide blocking layer is deposited on those parts of an integrated circuit, such as on an optical waveguide or a light scatterer, which are to be protected from damage by the deposition of salicide. The salicide blocking layer is used as one layer of the cladding of a silicon waveguide and a light scatterer.
    Type: Grant
    Filed: July 14, 2005
    Date of Patent: May 16, 2006
    Assignee: Luxtera, Inc.
    Inventors: Lawrence C. Gunn, III, Thierry J. Pinguet, Maxime Jean Rattier