Abstract: A graphics data form includes an information processing system having a generator for generating graphics images, each image comprising a recognizable representation of at least one real-life object. The GDF also includes a selector for selecting an image by a user of the system; a receiver for receiving information from the user; an associator for associating the information received with the selected image; a real time processor for manipulating how the image is presented; and a real time processor for processing data associated with the selected image responsive to manipulation of the selected image.

Abstract: An electrostatic discharge protection circuit for integration into an integrated circuit device. The protection circuit includes at least one transistor having a first terminal connected to an input or output terminal of the integrated circuit device, a second terminal connected to a supply line for the integrated circuit device, and a control terminal connected to ground. In a preferred embodiment, the transistor is formed by a structure that includes a substrate of a first conductivity type, a first region of a second conductivity type, a second region of the first conductivity type, a third region of the first conductivity type, and a fourth region of the second conductivity type. The third region has greater conductivity than the substrate and the fourth region has greater conductivity than the first region.

Abstract: This invention relates to a method for programming a Flash-EPROM type memory (1) comprising words of memory cells arranged in rows (23) and columns (31), in which a floating-gate transistor (7) acts as a storage device, the floating-gate transistors of the memory cells (2-9) in the same word (10) have their control gate connected to the same word line connection (30) and their source connected to the same main electrode (29) of a selection transistor (26), the other main electrode (28) of which is connected to a vertical word source connection (25), in which M memory cells (2, 2b) are programmed simultaneously in N different words (10, 200) during a single programming cycle, where M is less than the number P of memory cells in a word, and where M, N and P are integer numbers.

Abstract: In a differential amplifier with asymmetrical outputs, the gates of the two load transistors are at the same specified potential and the voltage at the connection node between the load transistor and the amplifier transistor of one arm is stabilized by means of a compensation structure. This amplifier works at low VCC (e.g., less than 2 volts) while at the same time having high gain.

Abstract: A device for demodulating a binary signal having a predetermined carrier frequency and phase-modulated by encoded pulses. The device includes a phase-locked loop circuit having a phase comparator followed by a low-pass filter and a voltage-controlled oscillator, which is voltage-controlled by the output of the filter. The voltage-controlled oscillator outputs a binary signal that is synchronous with the modulated signal and at a frequency N times the carrier frequency. The phase-locked loop circuit also includes a divider that divides by N the output signal of the oscillator and supplies the divided signal to one input of the phase comparator. Thus, a binary signal synchronous with the modulated signal and having a frequency equal to the carrier frequency is supplied to one input of the phase comparator. The other input of the phase comparator receives the modulated signal.

Abstract: An Exclusive-OR logic gate with four two-by-two complementary inputs and two complementary outputs. The structure of this Exclusive-Or gate is said to be symmetrical in that the gate has a propagation time that is identical whichever of the two pairs of complementary inputs is switched over, whatever the nature of the transition at output and whatever the logic state of the pair of inputs that do not switch over. The disclosed device enables a further reduction in the differences in the time taken for the propagation of the signal edges through the gate by eliminating the floating character of certain nodes. It also relates to a frequency multiplier comprising a tree of Exclusive-Or gates such as this.

Abstract: A boosted voltage driving circuit includes an inverter circuit with positive feedback and a selective breaking circuit. The selective breaking circuit disconnects the positive feedback from the output load during an operation phase of the boosted voltage driving circuit in order to reduce energy consumption. In a preferred embodiment, the boosted voltage driving circuit is the final stage of a decoder circuit for selecting and deselecting a line or column of a memory array, and the positive feedback is disconnected during a deselection phase in which the line or column is deselected. The present invention also provides a boosted voltage driving circuit that includes first, second, and third transistors and a selective breaking circuit. The first transistor is connected between a supply voltage and an output node, the second transistor is connected between the output node and ground, and the third transistor is connected between the supply voltage and the gate of the first transistor.

Abstract: A computer system includes a central processing unit (CPU) for providing computer output signals; a non-computational base transceiver coupled with the CPU. The base transceiver comprises an interface for communicating with the CPU; a modulator for receiving computer output signals and providing modulated signals representing said computer output signals; and a transmitter for receiving said modulated signals, and transmitting said modulated signals via wireless media; and a non-computational remote transceiver comprising: a receiver for receiving signals via wireless media; a transmitter for transmitting signals via wireless media.

Abstract: A Flash-EPROM type memory cell with a short read time and a "very low supply voltage." The memory cell has the additional advantage of using less power, therefore generating less heat and allowing a denser integrated circuit. The memory cell comprises a floating-gate transistor whose source is coupled to the drain of a selection transistor. The floating-gate transistor is in a depleted state when the memory cell is "erased." The read voltage applied to the control gate of the floating-gate transistor is substantially equal to a general supply voltage which is in the range of 1.5 volts. The gate of the selection transistor receives a bias voltage at least equal to its conduction threshold. The gate of the selection transistor can also receive a bias voltage higher than the read voltage, which will speed up the read time further. A Flash-EPROM incorporating this memory cell is also provided.

Abstract: A method for testing output connections of at least one driver circuit that drives a plasma display panel. According to the method, at least one output of the driver circuit is switched to a high level for a predetermined time period. The output of the driver circuit is switched to a low level, and the time to discharge the output of the driver circuit with a constant discharge current is measured. It is determined whether a capacitive load is connected to the output of the driver circuit based on the measured time to discharge. In one preferred method, these steps are repeated for each of the outputs of the driver circuit. A driver circuit for driving a plasma display panel is also provided. The driver circuit includes driver output stages, and means for selectively sinking a constant discharge current from the output of at least one of the driver output stages to ground.

Abstract: The disclosure relates to integrated circuits and, more particularly, to a power-on-reset circuit. The proposed circuit produces an inhibition signal when the power is turned on, this signal being interrupted after the supply voltage Vcc has reached a first threshold (VS1) (VS1). Furthermore, the circuit has means to re-trigger the inhibition signal when the supply voltage drops by a certain value, in doing so even if the supply voltage remains above the first threshold. The reliability of the integrated circuit is improved. The disclosed circuit is particularly applicable to the inhibition of the writing circuit of an EEPROM memory.

Abstract: A semiconductor device includes a chip forming an integrated circuit; a connection substrate; an internal coupling mechanism; and at least one optical communication system. The connection substrate comprises an external coupling mechanism for electrically coupling to a device other than the chip. The internal coupling mechanism electrically couples the integrated circuit to the external coupling mechanism. The at least one optical communication system comprises two optoelectronic parts. The first optoelectronic part is either an emitter or a receiver which is integrated into the chip and constitutes one component of the integrated circuit. The second optoelectronic part is borne by the connection substrate and is able to be externally connected to the connection substrate. The second optoelectronic part faces the first optoelectronic part and is capable of exchanging light signals with the first optoelectronic part.

Abstract: A semiconductor device includes first through fourth pads and first through third external connection leads, with the first external connection lead being a ground connection lead and the first and second pads being ground pads. First through fourth connection wires selectively connect the pads to the external connection leads. Additionally, a first ground line is connected to the first pad, a second ground line is connected to the second pad, a first protective diode connects the first ground line to the third pad, and a second protective diode connects the second ground line to the fourth pad. The first external connection lead is connected to the first pad via the first connection wire and to the second pad via the second connection wire, the third connection wire connects the third pad to the second external connection lead, and the fourth connection wire connects the fourth pad to the third external connection lead.

Abstract: A programmable non-volatile memory device has a plurality of rows of memory cells that are accessible through selection addresses, with the number of physical rows being greater than the number of rows that are addressable at a given time. An associating circuit associates selected physical rows of the memory device with selection addresses. The associating circuit includes an associative memory that has a programmable memory location for each physical row of the memory device, and each memory location in the associative memory has an address field and at least one state bit. In one preferred embodiment, in the read mode, a row of the memory device is selected when the corresponding memory location in the associative memory contains the received address and state bits indicating that the row stores valid data for the received address. A method of programming such a non-volatile memory device is also provided.

Abstract: A method for monitoring the operating temperature of a semiconductor device. The method comprising the steps of: placing a thermal coupling material between the bottom of the semiconductor device and the top of a printed circuit board for inserting the device thereinto; inserting a sensor so to be at least partially covered by the thermal coupling material; and measuring the temperature from the sensor within a predetermined time interval. In accordance with another aspect of the invention, an apparatus is described to carry out the above process.

Abstract: A semiconductor device having separated exchange mechanism comprises a chip forming an integrated circuit; a connection substrate; device connection points or balls; and at least one exchange mechanism. The connection substrate comprises an external connection mechanism. The device connection points or balls are distributed in the form of a matrix and are located between the juxtaposed faces of the chip and of the connection substrate. The device connection points are connected to the external connection mechanism. The exchange mechanism comprises two parts. The two parts are arranged so as to be separated from each other and capable of exchanging signals between each other, in one or both directions. The first part is physically coupled to the chip. The second part is physically coupled to the connection substrate and is connected to the external connection mechanism.

Abstract: A memory cell is provided that includes a transistor and a capacitor. The transistor has a gate, a drain, a source, and a back-plane gate, and the capacitor has first and second electrodes. The back-plane gate of the transistor is connected to the first electrode of the capacitor. In a preferred embodiment, the source of the transistor is also connected to the first electrode of the capacitor. Additionally, a memory cell is provided that includes a transistor and a capacitor. The transistor has a gate, a drain, a source, and a back-plane gate, and the capacitor has first and second electrodes. The first electrode of the capacitor is connected to the source of the transistor, and the back-plane gate changes the threshold voltage of the transistor in correspondence to charge stored on the capacitor. In one preferred embodiment, the back-plane gate is charged from the transistor by a tunneling process.

Abstract: In a communication network comprising at least one communication medium and a plurality of nodes, each node having a unique identifier associated therewith that is transmitted as part of each message transmitted by said node, a method for transmitting signals includes the following steps performed at a first node:(a) determining that a message is to be sent;(b) determining whether the communication medium is available for transmission of the message;(c) determining whether at least a second node is also attempting to transmit during a time period;(d) if at least a second node is also attempting to transmit during the time period, comparing the unique identifier of the first node with the unique identifier for the second node;(e) determining a transmission priority order based on said comparison; and(f) waiting for the second node to finish transmitting in the case that the second node has a higher priority than the first node.

Abstract: A method is illustrated the flow diagram 100 of FIG. 1. A processor 1001 renders a message 1025 for the processor operator's education during times of processor latency 1015 such as dialing onto any network such as the Internet. This wait time 1017 is normally non-productive and therefore can be used in such a way as to be non-invasive. It is also understood that this time is short so as to make other actions such as getting up from the desk not attractive. Finally even if the wait time was or became very short the present invention provides the first message 1025 to the process operator, that has been filtered. This filtering is a balance of the message owner's willingness to out bid other messages, the time of the day, the location of the operator, and finally the operator's likes and dislikes.

Abstract: A voltage boosting circuit for use in an integrated circuit having at least four driving voltage phases that include first and second voltage phases with amplitudes substantially equal to the supply voltage, and first and second boosted voltage phases. The voltage boosting circuit includes an input that receives the first or second voltage phase, an output that supplies the first or second boosted voltage phase, and a charge node that is coupled to the input. Additionally, a supply voltage precharge circuit precharges the charge node, and an additional transistor is connected between the supply voltage and the charge node. The additional transistor is driven by a voltage with a greater amplitude than the supply voltage so that the charge node is precharged up to the supply voltage and the first or second boosted voltage phase that is output by the voltage boosting circuit reaches an amplitude equal to substantially twice the supply voltage.