Abstract: An integrated circuit includes a microprocessor driven by an internal clock signal and at least one internal peripheral circuit activated selectively by the microprocessor to perform an operation, wherein said circuit includes a circuit for matching the period of the internal clock signal to the operating time of the activated internal peripheral circuit. The integrated circuit can be used as part of any microcontroller.

Abstract: In an information handling system, a relay server provides links for communicating with network resources, via a network comprising a plurality of network units, for client communication units having unsigned Java applets that request a network resource from a target remote server on the network. The request is a signal that identifies the target unit within the network as a source of said network resource. The relay server accomplishes this by establishing a double link between the unsigned applet and the target unit for providing at least the requested network resource.

Abstract: The invention proposes a method of selecting a determined access line of a serial access type integrated circuit memory, a determined access line being selectable among a determined group of access lines (AL0-AL7) of the same nature, for example a group of bit lines or a group of word lines, a line code on p bits being respectively associated to each access line of the group, which consists in pre-activating all the access lines of the group, then ofdeactivating progressively the other access lines as a function of the bits (Ai) of the line code of the access line to select received in series via the serial data input of the memory such that, in the end, only the access line to be selected remains activated.

Abstract: At a charging phase, a capacitor (PC) is charged through two complementary charging transistors (TR1, TR2) connected in series to a first terminal (T1) of the capacitor (PC). At a voltage multiplication phase, an input voltage (Vdd) is delivered to the second terminal (T2) of the capacitor and an output voltage (Vout), increased with respect to the input voltage, is recovered at the first terminal (T1) of the, capacitor, and the capacitor is discharged during a discharging phase. During three phases, the substrate (BK2) of the charging transistor (TR2) directly connected to the first terminal (T1) of the capacitor is slaved to the source (S2) of this same charging transistor (TR2), while still keeping the source-substrate junction and the drain-substrate junction of this charging transistor (TR2) reverse-biased.

Abstract: A semiconductor package having an encapsulation that encapsulates an integrated circuit chip and an external lead frame for the chip. Multiple connection leads project from the periphery of the encapsulation. At least one external face of the encapsulation is covered with a layer of electrically conductive material, and the conducting material layer has at least one lateral extension that electrically contacts at least one of the projecting connection leads. A method of manufacturing such a semiconductor package is also provided.

Abstract: A method to resize an image on a server comprising the steps of: hosting multimedia content on a server, wherein said server is coupled to one or more client systems capable of rendering multimedia content, wherein said multimedia content includes at least one image; receiving user requests to transmit user selected multimedia content; determining the display size directives of each image referenced on said user selected multimedia content; scaling said image referenced to the size specified in said multimedia content; and transmitting said user selected multimedia content with said image scaled to said size directive. A server for hosting multimedia content is electrically connected to one or more client systems for rendering multimedia content.

Abstract: A column register of an integrated circuit memory, notably in EEPROM technology, is utilized in a method of writing a data word of 2p bits in the memory, where p is a non-zero whole number. The method includes the following steps: 1) erasing all the cells of the word; 2) loading 2q data in 2q high-voltage latches (HV1, HV3, HV5, HV7), and loading 2p−2q other data in the 2p−2q low-voltage latches (LV0, LV2, LV4, LV6); and 3) programming 2q cells of the memory (M0, M2, M4, M6) as a function of the data memorized in the 2q high-voltage latches; as well as repeating 2p−q−1 times the following steps: 4) loading, in the 2q high-voltage latches, of 2q other data that were loaded in the 2q low-voltage latches at step 2); and 5) programming 2q other cells of the memory (M1, M3, M5, M7) as a function of the data memorized in the 2q high-voltage latches.

Abstract: A signature generator circuit is provided for generating a signature word relating to a plurality of words. The signature generator circuit includes a logic gate that receives the plurality of words in series at one input, and a shift register that has a data input, a clock input, and a register output. The clock input receives a clock signal that sets the rate of the plurality of words, the data input is coupled to the output of the logic gate, and the register output is coupled to another input of the logic gate. In a preferred embodiment, the shift register also has a parallel output for outputting the contents of the shift register. Also provided is a method for generating a signature relating to a plurality of words using a logic gate and a shift register. The contents of the shift register are reset. One of the words is supplied in series to the logic gate, at least one of the bits in the shift register is also supplied to the logic gate, and the output of the logic gate is stored in the shift register.

Abstract: A socket contact with Kelvin contact for the testing of IC devices comprising a plurality of conducting strip sets embedded across a non-conducting base. Each strip set includes two pairs of electrodes. Two pairs of electrodes are designed such that each pair functions to contact one of the two corresponding leads of an IC device. Within the pair, one electrode forms a connection between the IC lead and the tester, and the other electrode provides a Kelvin contact.

Abstract: A device for the programming of cells of an electrically programmable non-volatile memory. The device comprising a first reference input for receiving an erase signal for erasing one or more memory cells in the non-volatile memory and a second reference input for receiving an programming signal for programming one or more memory cells in the non-volatile memory. A regulation circuit coupled to the first reference input and coupled to the second reference input for regulating the magnitude of an erasure signal and for regulating the magnitude of a programming signal so that an electric field of approximate equal absolute magnitude is created on the floating gate of one or more memory cells during an erase type operation and an programming type operation.

Abstract: A monolithically integrated selector for electrically programmable memory cell devices can be switched at an output terminal (OUT) between a high voltage (HV) and a low voltage (LV). It comprises a leg (N2, N1) of fast ground discharge (GND) from the output terminal, a discharge control leg (P1, N3, N4) driving the selector switching through a phase generator (PHG).

Abstract: A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a substrate-on-insulator type semiconductor substrate having a lower portion on top of which there is an upper insulating layer. A first semiconductor block and a second semiconductor block are produced in the upper insulating layer, and decoupling means are arranged in the upper insulating layer between the first and second semiconductor blocks. The first semiconductor block defines a first capacitor with the lower portion of the substrate, the second semiconductor block defines a second capacitor with the lower portion of the substrate, and the decoupling means includes at least one semiconductor well that defines a decoupling capacitor with the lower portion of the substrate. The capacitance of the decoupling capacitor is higher than the capacitance of each of the first and second capacitors.

Abstract: A diaphragm-support disc for a polishing machine of the type in which a work piece to be polished is sandwiched between a radial front face of a diaphragm and a polishing surface or cloth. The diaphragm is extended across and wrapped around the peripheral edge of a radial front face of the disc, and a radial rear face of the diaphragm is subjected to pressure from a fluid. The diaphragm-support disc includes a main annular part that projects from the radial front face of the disc and is located in a peripheral region of the radial front face of the disc a predetermined distance from the peripheral edge of the radial front face of the disc. The main annular part can act on the work piece through the diaphragm so as to press the work piece onto the polishing surface or cloth by an axial displacement of the disc with respect to the polishing surface or cloth.

Abstract: A process for forming a low resistivity titanium silicide layer on the surface of a silicon semiconductor substrate. In the process, an effective amount of a metallic element such as indium, gallium, tin, or lead is implanted or deposited on the surface of the silicon substrate. A titanium layer is deposited on the surface of the silicon substrate, and a rapid thermal annealing of the titanium-coated silicon substrate is performed to form low resistivity titanium silicide. In preferred processes, the metallic element is indium or gallium, and more preferably the metallic element is indium. A semiconductor device that has a titanium silicide layer on the surface of a silicon substrate is also provided.

Abstract: A cache management system determines stack distance by determining the stack reuse distance, less the number of duplicate pages in the system trace. The stack reuse distance is defined as the number of references between the first reference to a datum and the next reference to the same datum. The stack reuse distance can be easily calculated by maintaining a count of data references in a stream. The system also recognizes that the number of duplicate pages in a cache can be approximated in a probabilistic manner, thereby improving the efficiency of the cache analysis. Stack distance can be approximated during normal system operation and stack analysis can be performed in a dynamic manner for optimal cache tuning in response to data reference workloads. Thus, the cache miss ratio curve is generated either from a system trace in an off-line mode, or in real time during normal system operation.

Abstract: A method on a data processing server for creating customizable electronic documents in a client-server computer network having one or more data processing servers electronically connected to a plurality of data processing clients. In one embodiment, the method provides the sender with the ability of defining, via one or more interface controls, which portions of an electronic bill are changeable and modifiable by one or more recipients. This permits the subsequent users the authority to only modify the fields as controlled by the sender. In another embodiment, the system permits tracking of changes made by each subsequent recipient of the bill compared with the original billing data. In another embodiment, the method provides the recipient a user preference file which controls how the bill is laid-out by the user.

Abstract: An integrated circuit sample package is provided for checking electrical functionality and alignment of a checking device. The checking device includes a contactor and equipment for checking mechanical and electrical features of at least one integrated circuit device. The integrated circuit sample package substantially reproduces the external envelope of the integrated circuit device and is manufactured from an electrical conducting material that is resistant to mechanical wear. In one preferred embodiment, the integrated circuit sample package includes a body that substantially reproduces the external envelope of the body of the integrated circuit device, and offshoots that substantially reproduce the external envelope of the terminals of the integrated circuit device. A method for checking electrical functionality and alignment of a checking device is also provided.

Abstract: A waveform track-and-hold circuit receives an analog input signal and generates an analog output signal. The waveform track-and-hold circuit includes a differential separating input stage, a differential separating output stage, first and second charge storage means, and switch means. The first and second charge storage means are coupled between the differential separating input stage and the differential separating output stage, and the switch means are controlled by a logic control signal so as to selectively isolate the first and second charge storage means from the analog input signal. Additionally, the differential separating input stage includes a push-pull input stage connected to the switch means and receiving the analog input signal. In a preferred embodiment, the analog input signal is supplied to the emitters of transistors that form the push-pull input stage, the collectors of the transistors are connected to the switch means, and the transistors are part of current mirror circuits.

Abstract: A fixture to hold an electronic substrate having probe areas on a top surface. The top surface of the electronic substrate is left open to provide a maximum area to couple interconnect wires for a device under test. In addition, a bottom surface of the substrate is left open to provide a maximum area to couple with a probe card in one embodiment, or a test head in another embodiment. This open bottom and open top minimize the mechanical interference with electrical connections. The substrate is planarized to a frame by one or more clamps that are attached to the frame. The clamps provide adjustment of the pressure down on the substrate in a Z-axis direction which is normal to the top surface of the substrate for providing a good connection with a planar card. In addition, the clamps provide adjustment in the an X-Y plane parallel to the frame and rotational correction about the Z-axis.

Abstract: A method of automatically selecting processing parameters for encoding digital content. Metadata containing the genre of the digital content, receiving the compression level selected for encoding the digital content is received. An algorithm selected for encoding the digital content is received. And a previously defined table to select the processing parameters for encoding the digital content based on the genre of the content, the compression level selected and the algorithm selected is indexed and the processing parameters are retrieved.