Abstract: In an information processing system, a method to perform I/O (Input/Output) operations for an interpretative based program that is executing on an Interpretative Machine (IM). The method comprises the steps of: executing an interpretative based program on an Interpretative Machine (IM); receiving a request to pass data of unknown length out of the program; allocating a local buffer in the information processing unit to write the data of unknown length; writing the data of unknown length to the local buffer; determining the size of the data of unknown length in the local buffer; and passing the length of the data combined with the data in the buffer out of the program. In accordance with another aspect of the invention, a computer readable medium is described to carry out the above method.

Abstract: A process for polishing, on a polishing machine and under defined polishing conditions, the external surface of at least one wafer of integrated circuits comprising a projecting feature covered over the entire surface of the wafer with an external layer of a material, consisting in calculating a main equivalent thickness equal to the main surface density of the projecting feature multiplied by the thickness of the latter; in polishing, under the defined polishing conditions, a reference wafer comprising an external layer of the material, having a uniform thickness and covering the surface of this reference wafer, so as to determine the rate of removal by the polishing machine corresponding to the ratio of the thickness removed to the polishing time elapsed; in calculating a polishing time equal to the ratio of the aforementioned equivalent thickness to the aforementioned rate of removal; in calculating a total equivalent thickness equal to the sum of the main equivalent thickness and of a complementary thickn

Abstract: A method is provided for generating a pulse signal with modulable-width pulses. A set-point signal is generated and compared with a control signal so as to produce the pulse signal. When the control signal is a two-state logical signal, a first reference voltage is taken as the set-point signal. When the control signal is a continuous analog voltage, the set-point signal is varied between the first reference voltage and a predetermined second reference voltage, which is higher than the first reference voltage. Also provided is a device for generating a pulse signal with modulable-width pulses. The device includes a set-point signal generator, a control signal generator, and a comparator that outputs the pulse signal. The set-point signal generator includes a first voltage source for generating a first reference voltage, and a second voltage source for generating a second reference voltage, which is higher than the first reference voltage.

Abstract: A processor that includes an instruction extraction stage, an instruction register, an instruction decoder, a first multiplexer that supplies the instruction register, and an autonomous counter with a presetting register. The first multiplexer receives the output of the extraction stage and the output of the instruction register, and the instruction decoder receives the output of the instruction register. Additionally, a first circuit produces a repetition signal if a received instruction is a repetition instruction, and a second circuit outputs a value from the received instruction to the presetting register when the received instruction is a repetition instruction. A third circuit produces an instruction execution signal that is supplied to the counter, and the first multiplexer is controlled so as to supply the instruction register based on a control output of the counter. The present invention also provides a method of handling instructions to be repeated by a processor.

Abstract: A method and apparatus for determining a referring entity for an access request for a node in a network comprises a plurality of nodes, wherein each node is identified by a unique address and each node comprises the capability for including sub-addresses. The method comprises the steps of: receiving a request for an address in the network, the request including a request for a sub-address within the node identified by the address; removing the sub-address from the request; comparing the sub-address received with a list of sub-addresses, each corresponding to a referring entity; and determining the referring entity corresponding to the request for an address based on the comparison.

Abstract: An Automated Intelligent Network (AIN) telephone system with a central office switching system. The AIN system includes a service provider system for providing customizable subscriber services based upon subscriber-specific data stored in an EMS database. The subscriber-specific data is selectively updated by a service provider. The AIN system further includes an intelligent peripheral system coupled with the central office switching system. The intelligent peripheral system includes a regional relational database for storing regional subscriber-specific data.

Abstract: A computer system includes a system bus, peripheral devices, bus control logic having bus control lines for bus master operation, and an allocation control circuit. The allocation control circuit is connected to at least one of the bus control lines and at least two of the peripheral devices. The connected bus control line is coupled to one of the connected peripheral devices by the allocation unit so that the one connected peripheral device can operate as a bus master on the system bus. In a preferred embodiment, the allocation control circuit includes switches that are controlled by the system software. Also provided is a method of allocating bus master control lines to peripheral devices. According to the method, the bus master control lines and the peripheral devices are connected to an allocation unit.

Abstract: A semiconductor device of the type having an integrated circuit with connection terminals connected to metal pads by connecting wires is provided. The integrated circuit includes a semiconductor substrate having a lower portion on top of which there is an upper layer that is more heavily doped than the lower portion. A first block and a second block are produced in the upper part of the substrate, and decoupling means are arranged in the vicinity of the first block. The decoupling means include at least one decoupling circuit that is connected to the lower portion of the substrate and to a ground connection pad, and the decoupling circuit has a minimum impedance at a predetermined frequency. In one preferred embodiment, the decoupling circuit includes an inductive-capacitive resonant circuit having a resonant frequency substantially equal to the predetermined frequency.

Abstract: The invention relates to a pulse generator circuitry for timing a low-power memory device of a type associated to a memory matrix, including a plurality of word lines driven by a row decoder, and a plurality of bit lines sensed by sense amplifiers. The matrix includes at least a dummy row and at least one dummy column. A delay chain of the pulse generator is formed by the dummy datapath of the memory matrix. The dummy datapath being defined by at least on dummy row and at least one dummy column. The datapath operates prior to the operation of the normal row and column path of the matrix. In another embodiment disclosed, the row decoder comprises a dummy row enable portion at the intersection between the dummy row and the dummy column. The delay chain includes at least the dummy row enable portion, the dummy row and the dummy column.

Abstract: A mechanism is provided that eliminates redundant components from objects of a program. Specifically, the mechanism is capable of detecting situations where a member of a given class is used by some, but not all instances of that class, and the elimination of this member from the instances where it is not needed. This is accomplished by an analysis of the program and its class hierarchy, followed by the construction of a new, specialized class hierarchy and a transformation of the program. These operations preserve the original behavior of the program, and have the effect of “optimizing away” unneeded class members from objects. The invention is also capable of replacing class hierarchies that exhibit virtual inheritance with class hierarchies that only exhibit nonvirtual inheritance, and is applicable across a broad spectrum of inheritance structures.

Abstract: Disclosed is a method and apparatus of securely providing data to a user's system. The data is encrypted so as to only be decryptable by a data decrypting key, the data decrypting key being encrypted using a first public key, and the encrypted data being accessible to the user's system, the method comprising the steps of: transferring the encrypted data decrypting key to a clearing house that possesses a first private key, which corresponds to the first public key; decrypting the data decrypting key using the first private key; re-encrypting the data decrypting key using a second public key; transferring the re-encrypted data decrypting key to the user's system, the user's system possessing a second private key, which corresponds to the second public key; and decrypting the re-encrypted data decrypting key using the second private key.

Abstract: In a communications system implementing Signaling System No. 7, the system comprising a link, a transmitter for transmitting digital data on the link, and a receiver; a communications method comprises: coupling to the link for receiving data; receiving data from the link; detecting an error condition of SS7 requiring the receiver circuit to operate in an octet counting mode; and initiating the counting of received octets, the counting beginning after detecting the error condition. The method can be implemented in a variety of ways, including without limitation, as a specially dedicated stand alone unit, as an adapter card in a computer system, or as a computer-readable medium such as a diskette or a digital transmission.

Abstract: A device for two-way digital transmission on a bus having at least one two-way line. The device includes a first pulling device for pulling a first section of the line to a first logic level, a second pulling device for pulling a second section of the line to the first logic level, and at least one two-way repeater that is connected between the first section and the second section. The repeater includes a third pulling device for pulling the first section of the line to a second logic level, a fourth pulling device for pulling the second section of the line to the second logic level, and a logic circuit that prevents the third and fourth pulling devices from being simultaneously active. In one preferred embodiment, at least one electronic circuit is connected to the first section of the line and at least one other electronic circuit is connected to the second section of the line.

Abstract: A voltage regulation device is provided for receiving a voltage at an input node and supplying a regulated voltage to electronic circuitry at an output node. The device includes a switching circuit that is coupled between the input node and the output node, and a control circuit that is coupled to the switching circuit. When the voltage level at the output node is below a threshold voltage, the control circuit controls the switching circuit so as to substantially short-circuit the input node and the output node. On the other hand, when the voltage level at the output node is not below the threshold voltage, the control circuit controls the switching circuit so as to substantially isolate the input node from the output node. In a preferred embodiment, the switching circuit includes an NMOS transistor, and the control circuit includes a differential amplifier that supplies a control signal to the gate of the NMOS transistor. A smart card containing a voltage regulation device is also provided.

Abstract: An address transition detector in a semiconductor memories, which provides means for obtaining two complementary address transition signals from an address signal and send them to a monostable circuit apt to emit output pulse signals on an output node as a function of logical status changements of said address signal, said monostable circuit comprising bistable memory circuits for storing the values of the address transition signals at each logical status changement of the adddress signal through a feedback path, said values of the address transition signals being apt to control selection means of the complementary address transition signals. According to the present invention, said monostable circuit (123; 223; 303; 403) has breaking means (140; 240; 340; 440) of the feedback path (FB) in response to an enable signal (AE).

Abstract: An activation signal generating circuit includes a combinational logic circuit and a switch. The combinational logic circuit receives a normal mode control signal and a test mode control signal, and the switch receives a periodic clock signal. The switch is controlled by the output of the combinational logic circuit such that an activation signal is generated from the periodic clock signal. In one preferred embodiment, the switch is a CMOS change-over switch having two complementary MOS transistors connected in parallel, and a potential setting circuit imposes a specified potential at the output of the switch when the switch is open. A method of generating an activation signal is also disclosed.

Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided.

Abstract: A carrier of semiconductor wafer transportation. The carrier comprising: a base; two or more walls mounted to the base, with a plurality of grooves for receiving wafers by lateral insertion thereinto through a mouth, the mouth defined by an upper wall and a substantially horizontal lower wall, wherein the groove comprises a closed end defined by a back wall joined to the upper wall and the lower wall so that the groove narrows from the mouth towards the closed end, the upper wall being slanted upward towards the mouth and the back wall being slanted towards the mouth in the region close to the horizontal wall.

Abstract: A circuit is provided for supplying a load from an AC voltage supply. The circuit includes a control circuit and a bidirectional switch coupled in series with the load. The bidirectional switch includes two one-way switches connected in antiparallel, and the control circuit controls the bidirectional switch based on a relatively low DC voltage. The bidirectional switch is connected to a first terminal of the AC voltage supply, and the DC voltage is referenced to the first terminal of the AC voltage supply. Additionally, an apparatus connected to an AC voltage supply and a relatively low DC voltage is provided. The apparatus includes a control circuit, a load to be supplied by the AC voltage supply, and a bidirectional switch coupled in series with the load. The bidirectional switch includes two one-way switches connected in antiparallel, and the control circuit controls the bidirectional switch based on the DC voltage.

Abstract: A semiconductor non-volatile memory device that includes memory cells and selection transistors. The memory cells each include a floating gate transistor having an active area, source and drain regions, a floating gate, and a control gate, and each of the floating gate transistors is serially coupled to one of the selection transistors. A contact to the control gate is located above the active area. In a preferred embodiment, the contact is substantially aligned with a central portion of the active area. A method for manufacturing a non-volatile memory device on a semiconductor substrate is also provided. According to the method, a poly1 layer is deposited, an interpoly dielectric layer is deposited above the poly1 layer, and a poly2 layer is deposited above the interpoly dielectric layer. A mask is provided to define the control gate, and a Self-Aligned poly2/interpoly/poly1 stack etching is used to define a gate stack structure that includes the control gate and the floating gate.