Abstract: An electroplating bath includes two electrolytes that are separated by a low ionic mobility barrier substance. Electroplating substrates can be transferred between the two electrolytes, through the barrier substance. Successive layers can be deposited by alternately electroplating in the two electrolytes. The substrate need not be brought through an air-liquid interface in transferring it between the two electrolytes. More than one anode can be provided in each electrolyte for depositing alloy film layers. A dummy electrode can be provided in each electrolyte to be used in lieu of the substrate in order to change concentrations of compounds in each electrolyte so that sharp compositional transitions between successive layers deposited on the substrate can be obtained.

Abstract: A driver circuit for driving a plasma display panel comprising a plurality of cells arranged in a matrix of lines and columns; comprising a set of driver output stages connected to line or column electrodes to which a first electrode of cells of a same line or a same column are connected, respectively. The driver circuit includes a detection device for detecting a short circuit between two or more of the outputs of the driver output stages. It allows to test for alignment faults in the flexible cable connecting together the driver module housing incorporating the driver circuit and the electrodes of the plasma display panel.

Abstract: A micro-pipeline type asynchronous circuit and a method for detecting and correcting soft error. The asynchronous circuit records in a first recording unit a signal output by a calculation unit and then records in a second recording unit the same signal delayed by at least the duration of the pulse of a soft error. The recorded signals then are compared in a comparer circuit. If they are identical, no soft error has been detected and the output signal is recorded after another delay that is longer than the pulse duration of the soft error, and a request signal is transmitted to a control unit of a next logic stage with a delay twice as long as the pulse duration of a soft error.

Abstract: A testing device for testing dynamic characteristics of an electronic circuit using serial transmissions. The circuit includes a multiplexing device and a demultiplexing device for implementing a serial link in the component or circuit. The testing device includes a transmitter for transmitting binary signals to the multiplexing device, a receiver for receiving binary signals from the demultiplexing device, and a link for selectively providing a coupling between the transmitter and the receiver. Additionally, a clock generator delivers a first clock signal to the transmitter and a second clock signal, which has a different frequency than the first clock signal, to the receiver. In one preferred embodiment, the clock generator includes a single programmable-frequency oscillator and a variable delay circuit. The programmable-frequency oscillator delivers the first clock signal and the variable delay circuit delays the first clock signal to deliver the second clock signal.

Abstract: A self-aligned double-polysilicon type bi-polar transistor with a heterojunction base comprises a semiconducting heterojunction region lying over an active region of a semiconductor substrate and over an isolating region delimiting the active region, and incorporating the intrinsic base region of the transistor. An emitter region situated above the active region and coming into contact with the upper surface of the semiconducting heterojunction region. A polysilicon layer forming the extrinsic base region of the transistor, situated on each side of the emitter region and separated from the semiconducting heterojunction region by a separation layer comprising an electrically conducting connection part situated just outside the emitter region. This connection part ensures an electrical contact between the extrinsic base and the intrinsic base.

Abstract: A sense amplifier of the type coupled to a reference bit line and at least one cell array bit line. The sense amplifier includes an amplifying stage and a current voltage conversion circuit that compare a reference current from the reference bit line and a cell current from the cell array bit line. The current-voltage conversion circuit includes a voltage setting circuit for setting predetermined voltages on the reference bit line and the cell array bit line, a load circuit for the reference bit line and the cell array bit line, and current mirror circuits for mirroring the reference current and the cell current into the amplifying stage. The load circuit for the reference bit line and the current mirror circuit for the reference current are different circuits, and the load circuit for the reference bit line includes a transistor that mirrors a predetermined current that is generated outside of the sense amplifier.

Abstract: A phase locked loop is provided that includes a phase comparator, a charge pump circuit, a loop filter, and a voltage controlled oscillator. The charge pump circuit includes two symmetric branches, feedback paths, and circuit breaking switches. Each of the symmetric branches has a constant current generator and a pulsed current generator, with one terminal of the loop filter being connected to one of the symmetric branches and the other terminal of the loop filter being connected to the other of the symmetric branches. The feedback paths control the constant current generators based on voltages at the terminals of the loop filter, and each of the circuit breaking switches couple one of the pulsed current generators and the corresponding terminal of the loop filter. The pulsed current generators supply a first current whose amplitude is proportional to an amplitude of a second current supplied by the constant current generators through the duty cycle of the first current.

Abstract: An adaptive system for optimizing the bandwidth of a communication link in a communications session is disclosed. The decision as to when bandwidth in a communication session is to be released, or added, is based on the actual user activity rather than on an a priori determination which may not reflect the actual workload. Additionally, this decision is based on the actual costs associated with maintaining, releasing, and/or establishing a communication link or additional bandwidth. The costs include both direct costs and opportunity costs. The algorithm can also adapt its decision making process to its own performance, using feedback information to determine if it is minimizing the costs involved.

Abstract: A transistor manufacturing process includes the formation, on a layer (15) that will form the base of the transistor, of a stack of an SiGe alloy layer (16), a silicon oxide layer (17) and a silicon nitride layer (18), so as to form in this layer, a false emitter (20), to form, in the layer (15) that will form the base, an extrinsic base region (22) and to siliconize the surface of this extrinsic base region, to cover the extrinsic base region (22) and the false emitter (20) with a silicon dioxide layer (24) which is chemically and mechanically polished down to the level of the false emitter (20), to etch the false emitter (20) in order to form a window (25) and to form, in the window (25) and on the silicon dioxide layer (24), a polysilicon emitter (27). This process has particular application to manufacturing heterojunction bipolar transistors.

Abstract: The present invention is a docking interface for portable electronic devices that feature at least a printed circuit board (PCB) contact and a set of spring loaded contact pins for facilitating the recharging of power source and transfer of data between the devices and their hosts. Because of the thickness of a PCB and the retraction of the spring loaded pins, the overall profile of the present invention is reduced to a minimum. At the same time, the reliability of the contact between the portable device and the docking station is assured. As such, the present invention offers an economical and reliable solution for docking interface in portable electronic devices that permit further reduction in size and weight without imposing constraints on the availability of increased functionality.

Abstract: A semiconductor memory cell having a word line, a bit line, a precharge line, an access transistor, and first and second cross-coupled inverters. The first inverter includes a first P-channel transistor and a first N-channel transistor, and the second inverter includes a second P-channel transistor and a second N-channel transistor. The access transistor selectively couples the bit line to an output of the first or second inverter, and one terminal of the first N-channel transistor is connected to the precharge line. In a preferred embodiment, a control circuit is provided that, during a writing operation, supplies data to be written to the memory cell to the bit line, supplies a pulse signal to the precharge line, and activates the word line. A method of writing data to a semiconductor memory cell that is coupled to a word line and single bit line is also provided.

Abstract: In an E-commerce method for selling digital content over the Internet an FTP-like protocol is provided to carry out the delivery (download) of a purchased digital content item from a server computer to a client computer operated by the purchaser. The FTP-like communication protocol provides for error recovery during the download that does not require restarting the download from the beginning. After the download is completed the integrity of the downloaded file is checked. And the result of the check is communicated to the server which records that the digital content item has been successfully delivered to the purchaser.

Abstract: A method for designing a processor core is provided. Configuration registers are programmed by providing a cell configured at either one or zero for each bit of the configuration registers. Each configured cell is a latch with a data input and control signal inputs for receiving a direct resetting command and a direct setting command, and is configured at either one or zero by inhibiting either the direct resetting command or the direct setting command. Further, writing into the cells is permitted only in a test mode. Also provided is a method for designing and programming a processor core of the type having configuration registers. According to this method, a non-programmed processor core is designed by providing one vacant cell for each bit of the configuration registers. The vacant cell has the same abstract as both cells configured at one and cells configured at zero.

Abstract: A method is provided for forming an on-screen display (OSD) for overlay on a video image. According to the method, colors that are to be used to display the OSD are stored in a color look-up table, and a coefficient of transparency is assigned to each line of pixels of the OSD before overlaying the OSD on the video image. In a preferred method, the colors are stored in the color look-up table as three significant values representing chrominance and luminance for each pixel of the OSD, and the assigned coefficients of transparency are stored in a programmable register. This provides a substantial memory space gain in the color look-up table, and thus the range of available colors can be very wide. A device for forming an OSD for overlay on a video image is also provided. The device includes a color look-up table that stores a color for each pixel of the OSD, and a transparency programming register that assigns a transparency level to each line of pixels of the OSD.

Abstract: A method is provided for controlling a capacitive charge pump. The charge pump is regulated by a regulating voltage when the supply voltage is greater than the regulating voltage. When the supply voltage is less than a triggering voltage, which is less than or equal to the regulating voltage, the charge pump is automatically supplied between the supply voltage and ground. In one preferred method, the charge pump has a first supply terminal connected to the supply voltage and a second supply terminal that is automatically grounded when the supply voltage is less than the triggering voltage. Also provided is a capacitive charge pump device that includes a charge pump having first and second supply terminals, a voltage regulator delivering a regulating voltage, a switch connected between the second supply terminal and ground, and switch control circuitry for automatically controlling the switch.

Abstract: A method for reducing disturbing effects of coupling between a first transmission/reception device and a second transmission/reception device that are each connected to a subscriber line. According to the method, a signal received on a reception path of the first device is delayed by a delay equal to p times the transmission period. A coupling signal relating to a transmission path of a second device and the reception path of the first device is estimated based on a signal transmitted over the transmission path of the second device, and the delayed signal is ridded of the estimated coupling signal. Additionally, a device for transmitting/receiving a signal is provided. The device includes a memory coupled to a reception path for temporarily storing p symbols, a subtraction circuit, and a coupling estimation block.

Abstract: A structure is provided for a user-manipulable input device, such as an in-keyboard, joystick-type device, for allowing a user to provide input to a computer graphical user interface (GUI). The structure includes a user-manipulable, articulating member, and a plurality of stationary, electrically conductive sensors. The articulating member also has an electrically conductive member. The physical disposition of the articulating member and the sensors provides narrow gaps, across which are measurable capacitances. As the user manipulates the articulating member, the capacitances change in value. Circuitry produces signals related to the capacitances, and the signals are processed, according to a transfer function, to generate GUI input signals. The sensors are preferably sensing electrodes, incorporated into a circuit board. The articulating member is preferably a cone-shaped member, having a conductive surface which faces the sensors.

Abstract: A system and method of distributed metadata searching is disclosed. The present invention permits an extension of the searching and retrieval functions of existing Internet web search engines by utilizing computational resources embodied in user computer systems and search browsers. By distributing the searching and scanning functions to the user level, the present invention reduces the computational and communications burden on Internet web search engines and crawlers, resulting in lower computational resource utilization by Internet search engine providers. Given the exponential growth rate currently being experienced in the Internet community, the present invention provides one of the few methods by which complete searches of this vast distributed database may be performed.