Abstract: A mechanism is provided for increased availability of input/output (I/O) drawers during concurrent I/O hub repair. The illustrative embodiments provide an alternative cabling scheme between an I/O planar and a plurality of I/O hubs that facilitates the I/O drawers being available even when an I/O hub fails. With this cabling scheme, a hypervisor or other virtualization mechanism configures routing tables in the firmware of the host system to cause data to be sent/received through the I/O hubs. In the event of a failure of an I/O hub, the routing tables may be updated by the hypervisor to utilize a different I/O hub coupled to the I/O drawer. By virtue of the modified cabling scheme of the illustrative embodiments, such updating of the routing tables allows I/O operations to continue at a single loop, or single barrel, throughput via the other I/O hub.

Abstract: A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory hub device integrated in a memory module. The memory system includes a first memory device data interface integrated in the memory hub device that communicates with a first set of memory devices integrated in the memory module. The memory system also includes a second memory device data interface integrated in the memory hub device that communicates with a second set of memory devices integrated in the memory module. In the memory system, the first set of memory devices are separate from the second set of memory devices. In the memory system, the first and second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.

Abstract: A memory system is provided that supports partial cache line read operations to a memory module to reduce read data traffic on a memory channel. The memory system comprises a memory hub device integrated in the memory module and a set of memory devices coupled to the memory hub device. The memory hub comprises burst logic integrated in the memory hub device. The burst logic determines an amount of read data to be transmitted from the set of memory devices and generates a burst length field corresponding to the amount of read data. The memory hub also comprises a memory hub controller integrated in the memory hub device. The memory hub controller controls the amount of read data that is transmitted using the burst length field. The memory hub device transmits the amount of read data that is equal to or less than a conventional data burst amount of data.

Abstract: A method mechanism is provided for communication between host systems using a transaction protocol and shared memories. Shared memories are initialized based on a discovery process in a communication fabric such that at least one endpoint has address ranges in shared memories of at least two host systems. A transaction oriented protocol may be established for using the shared memories of the host systems to communicate between root complexes and endpoints of the same or different host systems. The transaction oriented protocol specifies a series of transactions to be performed by the various elements, e.g., root complex or endpoint, to push or pull data. Various combinations of push and pull transactions may be utilized.

Abstract: A method, computer program product, and system are provided for dynamically routing data through the data processing system. Data is received at a first processor that is to be transmitted to a destination processor. The data that is received includes address information. A lookup is performed in routing table data structures based on the address information to identify candidate paths through which the data is routed to the destination processor. A determination is made as to whether any of the candidate paths are not able to be used to route the data to the destination processor based on a setting of at least one identifier. A path is selected from the identified candidate paths for routing of the data based on a setting of the at least one identifier. Then, the data is transmitted from the first processor along the selected path toward the destination processor.

Abstract: A memory system is provided that enhances the memory bandwidth available through a memory module. The memory system includes a memory controller and at least one memory module coupled to the memory controller. In the memory systems, each memory module comprises at least one memory hub device integrated in the memory module. In the memory system, each memory hub device in the memory module comprises a first memory device data interface that communicates with a first set of memory devices and a second memory device data interface that communicates with a second set of memory devices. In the memory system, the first set of memory devices which are separate from the second set of memory devices are communicated with by the memory hub device via the separate first and second memory device data interfaces.

Abstract: A mechanism is provided for communication between host systems using a queuing system and shared memories. Memory address spaces of the host systems are initialized such that endpoints may be accessible by root complexes across host systems. These memory address spaces may then be used to allow system images, and their corresponding applications, associated with these root complexes to communicate with the endpoints using a queuing system. Such a queuing system may comprise queue structures having doorbell structures for providing information about the queue entries in the queue structures. Queue elements may be generated and added to the queue structures, and the doorbell structure may be written to, in order to thereby inform an endpoint or root complex that queue elements are available for processing. DMA operations may be performed to retrieve the queue elements and the data corresponding to the queue elements.

Abstract: A mechanism is provided for transmitting data in a data network. A first processor of the data network receives data to be transmitted to a second processor within the data network. A determination is made if the data has previously been routed through an indirect communication link from a source processor, the indirect communication link being a communication link that does not directly couple the source processor to a final destination processor which is to receive the data. A communication link is selected over which to transmit the data from the first processor to the second processor based on results of determining if the data has previously been routed through an indirect communication link. Finally, the data is transmitted from the first processor to the second processor using the selected communication link.

Abstract: A cache, system and method for reducing the number of rejected snoop requests. A “stall/reorder unit” in a cache receives a snoop request from an interconnect. Information, such as the address, of the snoop request is stored in a queue of the stall/reorder unit. The stall/reorder unit forwards the snoop request to a selector which also receives a request from a processor. An arbitration mechanism selects either the snoop request or the request from the processor. If the snoop request is denied by the arbitration mechanism, information, e.g., address, about the snoop request may be maintained in the stall/reorder unit. The request may be later resent to the selector. This process may be repeated up to “n” clock cycles. By providing the snoop request additional opportunities (n clock cycles) to be accepted by the arbitration mechanism, fewer snoop requests may ultimately be denied.

Abstract: A system and method to manage device access in a software partition are provided. The illustrative embodiments provide a mechanism for exporting resources/devices from an administrator partition to a software partition in its purview. A trusted device list data structure is provided that identifies which devices are permitted to be exported into a software partition from an administrative partition. This trusted device list data structure also identifies which of the devices in the list of devices should be exported by default when exporting devices to a software partition, i.e. if no overrides are specified. In addition, a user-specifiable mechanism to override the entries in the trusted device list data structure is provided. For security purposes, this mechanism may not be used to export devices not listed in the trusted device list data structure. The mechanism may also be used to prevent the exporting of devices which are exported by default.

Abstract: A method, computer program product, and system are provided performing a Message Passing Interface (MPI) job. A first processor chip receives a set of arrival signals from a set of processor chips executing tasks of the MPI job in the data processing system. The arrival signals identify when a processor chip executes a synchronization operation for synchronizing the tasks for the MPI job. Responsive to receiving the set of arrival signals from the set of processor chips, the first processor chip identifies a fastest processor chip of the set of processor chips whose arrival signal arrived first. An operation of the fastest processor chip is modified based on the identification of the fastest processor chip. The set of processor chips comprises processor chips that are in one of a same processor book or a different processor book of the data processing system.

Abstract: The present solution addresses the need to carry out reorganization of a database storage. A statistics-based reorganization check procedure is performed on at least first database tables and indexes, resulting in a preliminary reorganization recommendation. Information on workload on tables and indexes of said database storage is received. Based on the information on workload and the preliminary reorganization recommendation, it is decided whether to carry out reorganization of the database storage in accordance with the preliminary reorganization recommendation.

Abstract: A mechanism is provided for providing reliability of communication. A first processor determines a current state of links coupled to ports of a first processor of the data processing system. Each port of the first processor comprises a plurality of links to a corresponding port on a second processor of the data processing system. The current state of the links indicates a level of error associated with each link. The first processor determines, for each link, if a level of error associated with the link exceeds a threshold. For each link whose level of error exceeds the threshold, the first processor tags the link with an error identifier in a switch associated with the ports of the first processor. The first processor reduces a level of usage for transmitting data on ports associated with links tagged with the error identifier.

Abstract: A reference monitor that authorizes information flows between elements of a data processing system is provided. The elements of the data processing system are associated with security data structures in a reference monitor. An information flow request is received from a first element to authorize an information flow from the first element to a second element. A first security data structure associated with the first element and a second security data structure associated with the second element are retrieved. At least one set theory operation is then performed on the first security data structure and the second security data structure to determine if the information flow from the first element to the second element is to be authorized. The security data structures may be labelsets having one or more labels identifying security policies to be applied to information flows involving the associated element.

Abstract: A mechanism is provided for translating text into visual imagery content. A request is received to identify at least one image associated with a text value. At least one association category from a plurality of association categories is identified with which to perform a search. A data structure is searched, using the at least one association category, for an identification of the at least one image that is associated with the text value. The at least one image is a visual representation of the text value. At least one image is retrieved in response to identifying at least one image associated with the text value. The at least one image is presented in a graphical user interface to a user.

Abstract: A mechanism is provided for transparent multi-hit correction in associative memories. A content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.

Abstract: A mechanism is provided for a one card to filter false signals due to a another card being hot-plugged. A discriminator circuit in the card receives a low-state signal via an input and, responsive to receiving the low-state signal, the discriminator circuit compares the low-state signal to a static signal. Responsive to the low-state signal being greater than the static signal, the discriminator circuit outputs a high-voltage signal. The high-voltage signal output by the discriminator circuit indicates that the low-state signal is a false low signal. Responsive to the low-state signal being less than or equal to the static signal, the discriminator circuit outputs a low-voltage signal. The low-voltage signal output by the discriminator circuit indicates that the low-state signal is a valid low signal.

Abstract: A compiler implemented software cache is provided in which non-aliased explicitly fetched data are excluded are provided. With the mechanisms of the illustrative embodiments, a compiler uses a forward data flow analysis to prove that there is no alias between the cached data and explicitly fetched data. Explicitly fetched data that has no alias in the cached data are excluded from the software cache. Explicitly fetched data that has aliases in the cached data are allowed to be stored in the software cache. In this way, there is no runtime overhead to maintain the correctness of the two copies of data. Moreover, the number of lines of the software cache that must be protected from eviction is decreased. This leads to a decrease in the amount of computation cycles required by the cache miss handler when evicting cache lines during cache miss handling.

Abstract: A mechanism is provided for booting a multiprocessor device based on selection of encryption keys to be provided to the processors. With the mechanism, a security key and one or more randomly generated key values are provided to a selector mechanism of each processor of the multiprocessor device. A random selection mechanism is provided in pervasive logic that randomly selects one of the processors to be a boot processor and thereby, provides a select signal to the selector of the boot processor such that the boot processor selects the security key. All other processors select one of the one or more randomly generated key values. As a result, only the randomly selected boot processor is able to use the proper security key to decrypt the boot code for execution.

Abstract: A mechanism is provided for masking a boot sequence by providing a dummy processor. With the mechanism, one of the processors of a multiprocessor system is chosen to be a boot processor. The other processors of the multiprocessor system execute masking code that generates electromagnetic and/or thermal signatures that mask the electromagnetic and/or thermal signatures of the actual boot processor. The execution of the masking code on the non-boot processors preferably generates electromagnetic and/or thermal signatures that approximate the signatures of the actual boot code execution on the boot processor. One of the non-boot processors is selected to execute masking code that is different from the other masking code sequence to thereby generate a electromagnetic and/or thermal signature that appears to be unique from an external monitoring perspective.