Abstract: A wide band, wide operating range, general purpose digital phase locked loop (PLL) runs in the digital domain except for the associated Time Digitizer (T2D) and Digitally-Controlled-Oscillator (DCO). By calibrating the T2D and DCO on the fly, a constant PLL loop BW is achieved by using the calibrated Phase Frequency Detection (PFD) and DCO information to normalize the control loop correction regardless of the input clock frequency, power supply voltage, processing and temperature variations. PLL loop BW is completely decoupled from the operating conditions and semiconductor device variation. This means that the PLL loop BW can be chosen very aggressively to reject the noise, thus achieving a low jitter, high performance PLL. Furthermore, since this PLL can reliably operate over a wide operating range, it is a one-design-fits-all general purpose PLL.

Abstract: A station capable of receiving information containing Walsh coding for a plurality of channels and canceling interference from the received information and the method of cancellation. A memory is provided for storing received signals containing a Walsh code for each of a plurality of channels as well as reflected and/or refracted versions of said received signals and a first plurality of signal paths is provided which are selectively coupled to the memory. The signal paths apply corresponding delays and inverse Walsh code transformations to separate the channels. Further, cancellation of the channels interfering with a desired channel proceeds with complementary delays and Walsh code transformation to regenerate the interference which is subtracted from the received signal in memory.

Abstract: A mobile telephone system and method having a base station for receiving data bursts during consecutive frames, each frame of predetermined time duration and divided into a plurality of slots of predetermined time duration. The base station has an antenna, base station electronics and preprocessing circuitry coupled to the base station antenna and the base station electronics. Delay circuitry is coupled to the base station preprocessing circuitry and base station electronics to provide the complement of a total time delay to the data bursts through the preprocessing circuitry and the delay circuitry equal to an integral number of the predetermined time duration of a frame. The time delay of the preprocessing circuitry can be fixed or variable, in which case the time delay of the delay circuitry is either fixed or variable, respectively.

Abstract: A method is disclosed for the improvement of BiCMOS or CMOS manufactured device performance, specifically bipolar junction transistor performance, in a cost effective manner. The method provides for fewer masking operations during bipolar junction transistor formation, in a CMOS flow process, yet also provides for the bipolar junction transistor to be optimized.

Abstract: A method for reducing total code size in a processor having an exposed pipeline may include the steps of determining a latency between a load instruction, and a using instruction and inserting a NOP field into the defining or using instruction. When inserted into the load instruction, the NOP field defines the following latency following the load instruction. When inserted into the using instruction, the NOP field defines the latency preceding the using instruction. In addition, a method for reducing total code size during branching may include the steps of determining a latency following a branch instruction for initiating a branch from a first point to a second point in an instruction stream, and inserting a NOP field into the branch instruction.

Abstract: A method and circuit for verifying the burst-mode operation and the frequency characterization of a self-timed sequential circuit 2 in burst mode by detecting and measuring an output 15 of the self-timed sequential circuit 2.

Abstract: A surface plasmon resonance (SPR) sensor (10) is disclosed. The sensor (10) includes a light source (18) and polarizer (20), which emit polarized light toward a surface plasmon layer (22). Light is reflected from the surface plasmon layer (22) at many angles, toward a photodetector array (26) via a mirror surface (24). The surface plasmon layer (22) includes a resonance film (30), such as gold, and a hard protective layer (32). The hard protective layer (32) is of a thickness below the sensing range (R) of the SPR sensor (10), and protects the resonance film (30) from damage. Materials useful as the hard protective layer (32) include silicon carbide (SiC), diamond-like carbon (DLC), silicon dioxide, silicon nitride, titanium oxide, titanium nitride, aluminum oxide, aluminum nitride, beryllium oxide, and tantalum oxide.

Abstract: An operational amplifier circuit includes: a first differential pair 20 of a first conductivity type having a first current branch and a second current branch; a second differential pair 22 of a second conductivity type having a first current branch and a second current branch; a first current mirroring device MP11 and MP26 coupled between the first branch of the first differential pair 20 and the second branch of the second differential pair 22 for combining the currents from these two branches; and a second current mirroring device. MN22 and MN24 coupled between the first branch of the second differential pair 22 and the second branch of the first differential pair 20 for combining the currents from these two branches.

Abstract: A dynamic random access memory (DRAM) device comprises a substrate, a plurality of substantially parallel word lines, and a plurality of substantially parallel bit lines. A plurality of memory cells are formed at intersections of the word lines and bit lines. Each of the memory cells includes a pillar of semiconductor material which extends outward from the substrate. A storage node plug extends from a storage node through the pillar to a storage node contact and one of a drain and a source of a MOS transistor. A bit line plug extends from the bit line inwardly to the outer surface of the pillar to form a bit line contact and the other of the drain and the source of the MOS transistor. A word line plug extends from the word line through the pillar and a portion of the word line plug forms a gate of the MOS transistor. The storage node plug, bit line plug, and word line plug can be formed asymmetrically as substantially solid, unitary structures having a desired thickness for ease in manufacturing.

Abstract: A MOSFSET structure with high-k gate dielecttrics for silicon or metal gates with gate dielectric liquid-based oxidation surface treatments prior to gate material desposition and gate formation.

Abstract: Methods are described for fabricating MOS type transistors, in which multiple drain extension implants are performed using different dopant species of the same type. The implanted drain extension dopants are activated using separate anneal processes to provide active dopants of both species throughout the drain extension regions adjacent the transistor channel.

Abstract: A method for extracting blanket (qual) polish rates from interferometry signals off patterned (product) wafer polish during non-enpointed CMP. The method includes estimating polish rates using polish data near the end of the polish period. Non-linear regression and iterative optimization is presented to extract relevant information. The processing includes least square processing step (43), determining the search fit (44) and determining if this is the best fit (45).

Abstract: A probe having a built-in reference plane for use with TDR testing includes a conductive sheet member such as a wire mesh which is attached to a ground input of a TDR system. The conductive sheet is located proximate the tip of the test probe and extends radially from an axis of the test probe thereby providing its own reference ground plane.

Abstract: A charge pump circuit is configured for charging of parasitic capacitances associated with charge pump capacitors in a manner that minimizes voltage ripple. The charge pump circuit is suitably configured with an independent charging circuit configured for supplying the current needed to charge the parasitic capacitances, rather than utilizing the reservoir capacitor to supply the needed current. The independent charging circuit can be implemented with various configurations of charge pump circuits, such as single phase or dual phase charge pumps, and/or doubler, tripler or inverter configurations. The independent charging circuit includes a parasitic charging capacitor or other voltage source configured with one or more switch devices configured to facilitate charging of the parasitics during any phases of operation of the charge pump circuit.

Abstract: A high-performance, high I/O ball grid array substrate, designed for integrated circuit flip-chip assembly and having two patterned metal layers, comprising: an insulating layer having a first surface, a second surface and a plurality of vias filled with metal. Said first surface having one of said metal layers attached to provide electrical ground potential, and having a plurality of electrically insulated openings for outside electrical contacts. An outermost insulating film protecting the exposed surface of said ground layer, said film having a plurality of openings filled with metal suitable for solder ball attachment. Said second surface having the other of said metal layers attached, portions thereof being configured as a plurality of electrical signal lines, further portions as a plurality of first electrical power lines, and further portions as a plurality of second electrical power lines, selected signal and power lines being in contact with said vias.

Abstract: The present invention provides a semiconductor device 200 having a localized halo implant 250 located therein, a method of manufacture therefore and an integrated circuit including the semiconductor device. In one embodiment, the semiconductor device 200 includes a gate 244 located over a substrate 210, the substrate 210 having a source and a drain 230 located therein. In the same embodiment, located adjacent each of the source and drain 230 are localized halo implants 250, each of the localized halo implants 250 having a vertical implant region 260 and an angled implant region 265. Further, at an intersection of the vertical implant region 260 and the angled implant region 265 is an area of peak concentration.

Abstract: The present invention provides a capacitor 300, a method of manufacture therefor and an integrated circuit including the same. In one embodiment of the invention, the capacitor 300 includes a first conductive plate 320 located over a semiconductor substrate 310, wherein the first conductive plate 320 has a second conductive plate 340 located thereover. The capacitor 300, in the same embodiment, further includes a dielectric layer 330 located between the first conductive plate 320 and the second conductive plate 340, wherein the dielectric layer 330 includes a Group 17 element.

Abstract: Systems and methodologies are disclosed for interfacing a storage medium with a host using a segmented buffer. Data blocks are transferred between the host and medium according to logical block addresses, with buffer segment pointers indicating the logical block addresses of data blocks in the buffer. Buffer management hardware or firmware compares the pointer values directly with logical block addresses from host commands in order to determine whether desired data blocks are within the buffer.

Abstract: A method of reducing by-product deposition inside wafer processing equipment includes providing a chamber having a peripheral inner wall and placing a semiconductor wafer within the chamber. The method also includes placing a ring within the chamber proximate the peripheral inner wall and introducing a plurality of reactant gases into the chamber and reacting the gases. The method also includes introducing a heated gas into the chamber through the ring proximate the peripheral inner wall to increase the temperature of the peripheral inner wall.

Abstract: A method is provided for forming dual work function gate electrodes. A dielectric layer is provided outwardly of a substrate. A metal layer is formed outwardly of the dielectric layer. A silicon-germanium layer is formed outwardly of the metal layer. A first portion of the silicon-germanium layer is removed to expose a first portion of the metal layer, with a second portion of the silicon-germanium layer remaining over a second portion of the metal layer. A silicon-germanium metal compound layer is formed from the second portion of the silicon-germanium layer and the second portion of the metal layer. A first gate electrode comprising the first portion of the metal layer is formed. A second gate electrode comprising the silicon-germanium metal compound layer is formed.