Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).

Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of real-time information but also sends diversity packets at the diversity rate as increased (d22).

Abstract: A combined channel and entropy decoder is provided that achieves a significant bit-error rate improvement using likelihood values (61) instead of conventional bits. The likelihood values are stored in a buffer (62). A unique code-word is searched in the bit pattern or in the likelihood value. When a unique code-word is found at the identifier (63), candidate code-words are loaded into computation units where each unit computes code-word likelihood for a given code-word bit pattern. The code-word likelihood values are compared and the selected code information is fed back to the code-word controller 67 to proceed to the next-step decoding.

Abstract: A robust, reliable and low-cost metal structure and process enabling electrical wire/ribbon connections to the interconnecting copper metallization of integrated circuits. The structure comprises a layer of barrier metal that resists copper diffusion, deposited on the non-oxidized copper surface in a thickness such that the barrier layer reduces the diffusion of copper at 250° C. by more than 80% compared with the absence of the barrier metal. The structure further comprises an outermost bondable layer which reduces the diffusion of the barrier metal at 250° C. by more than 80% compared with the absence of the bondable metal. Finally, a metal wire is bonded to the outermost layer for metallurgical connection. The barrier metal is selected from a group consisting of nickel, cobalt, chromium, molybdenum, titanium, tungsten, and alloys thereof. The outermost bondable metal layer is selected from a group consisting of gold, platinum, and silver.

Abstract: An integrated circuit has a built-in self-test (BIST) arrangement (60). The built-in self-test arrangement includes a read only memory (ROM), (140) that stores test algorithm instructions. A ROM logic circuit (410) receives an instruction read from the read only memory and produces a group of output signals dependent upon the instruction. A BIST register 420 receives and stores the group of output signals from the logic circuit for controlling self-test of the integrated circuit.

Abstract: A capacitor under bitline DRAM memory cell and method for its fabrication provides a high density memory cell with the capacitor formed in the PMD layer. The memory cell utilizes several variations of storage contact pillar structures as, for example, a storage plate of the memory cell capacitor formed within a trench in the PMD layer. This capacitor plate structure is overlaid with a capacitor dielectric layer which is overlaid with another conductive layer, for example, the M1 layer to form the other capacitor plate. An access transistor formed between substrate active regions and a word line, is in electrical communication with a bit line contact, the storage contact capacitor plate, and the word line respectively. The high density memory cell benefits from the simple standard processes common to logic processes, and in one embodiment requiring only one additional masking step.

Abstract: A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a transistor base. The base current compensation circuit is configured to inject current into the base of the transistor without the headroom requirements, as well as being less complex than other approaches. An exemplary base current compensation circuit comprises a sampling circuit and a current mirror feedback circuit configured for providing multiples of the base current demanded by the transistor device.

Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of real-time information but also sends diversity packets at the diversity rate as increased (d22).

Abstract: According to one embodiment of the present invention, a system (10) for data transfer is disclosed that comprises a transfer memory (24) having one or more buffers (40, 42, 44, 46, and 48). Accessing units comprising direct memory access units (20 and 22) are coupled to the transfer memory (24) and are operable to access the transfer memory (24). Pointers (50, 52, and 54) stored in the transfer memory (24) direct the accessing units (20 and 22) to selected ones of the buffers (44, 46, and 48) such that no two accessing units (20 and 22) are simultaneously accessing one buffer (44, 46, and 48). More specifically, the pointers (50, 52, and 54) may also direct a memory control unit (30) to a buffer that is not being accessed by an accessing units (20 and 22). According to one embodiment of the present invention, a method for data transfer is disclosed. First, a transfer memory (24) comprising one or more buffers (40, 42, 44, 46, and 48) is provided.

Abstract: A substrate (110) for an unpackaged integrated circuit (IC) chip (118). The substrate comprises an insulative material (112), a plurality of contacts (114) disposed thereon, and a conductive ring (150) disposed around the outer perimeter of the contacts (114). Conductive traces (115) may be disposed around one or more contacts (114) and may be coupled to the conductive ring (150). An electro-less plating technique is utilized to plate contacts (114), avoiding unnecessary conductive material such as plating stubs being included in the contact (114) pattern, reducing interference. The conductive ring (150) shields the chip (118) from interference.

Abstract: A surface treatment for porous silica to enhance adhesion of overlying layers. Treatments include surface group substitution, pore collapse, and gap filling layer (520) which invades open surface pores (514) of xerogel (510).

Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.

Abstract: A transconductance circuit (16) and method for protecting an H-bridge power circuit (10) that provides power to a load that includes an inductive component (14) connected between one side of the inductive component (14) and a gate (25) of a low side transistor (24) of the H-bridge (10). The transconductance circuit (16) operates to pull current from the inductive component (14) to ground (30) when the inductive load (14) sources current to a body diode of the high side transistor (20). The transconductance circuit (16) creates a regulated voltage to the gate (25) of the low side transistor (24) to cause the low side transistor (24) to conduct the current away in a regulated manner from the inductor (14) and the high side transistor (20) to ground (30).

Abstract: A write current circuit (40) adapted to drive a thin film write head (L0) of a mass media information storage device. The write current circuit includes a write current reference voltage circuit (42) adapted to selectively establish amplitude of a write current signal. The write current circuit further includes programming circuitry (M5-M10) driven such that several parameters of the write current waveform can be controlled, including the write current amplitude, overshoot amplitude and overshoot duration. The present invention achieves technical advantages by providing the ability to both produce an accurate write current, and also providing the ability to establish the write current waveform shape so that customers can optimize disk drive performance even when using different thin film write heads available from different suppliers.

Abstract: Using deuterium oxygen during stream oxidation forms an oxidizing vapor. Since deuterium is chemically similar to hydrogen, the oxidation process takes place normally and the silicon-silicon oxide interface is concurrently saturated with deuterium. Saturating the interface with deuterium reduces the interface trap density thereby reducing channel hot carrier degradation.

Abstract: After via etch, a low-k dielectric layer (104) is treated with an in-situ O2 plasma. Resist poisoning is caused by a N source that causes an interaction between low-k films (104), such as OSG, and DUV resist (130, 132). The in-situ plasma treatment immediately removes the source of poisoning to reduce or eliminate poisoning at trench patterning.

Abstract: A forward biased diode 40 is used to charge up a photodiode 26 rather than an NMOS transistor. This photodiode charging mechanism increases the dynamic range and optical response of active pixel arrays, and improves the scalability of the pixel element.

Abstract: A circuit (16,86) provides digital signals indicative of slew rates of phase signals (220) of H-bridge power drive transistors (60,62,64) of motor windings (66) of a mass data storage device (10). The circuit uses up and down phase control signals (UP,DN) to initiate up and down voltage changes in the motor phase signals. A portion of the circuit (180) produces a state change in a phase status output signal (196) when the phase signal (220) is less than a supply voltage (186). A digital comparison circuit (210) compares the phase status output signal (196) and the up and down control signals (UP,DN), and produces respective rise and fall digital outputs (216,217) when the up and down phase control signals and the phase status output signal are the same. The respective rise and fall digital outputs (222,224) have state change timings that indicate rise and fall times of said motor phase signals (220).

Abstract: While the manufacturing of integrated circuits (IC) has become a mostly automated process, the loading of the ICs into storage and shipping tubes 105 still requires a large amount of human interaction. A major stumbling block to the automation is the removal and insertion of retention pins 115 in the tubes. The present invention uses pressurized air 406 to hold a partially extracted retention pin 115 in position while the tube 105 is loaded. Once loaded, the retention pin 115 is reinserted. By not fully extracting the retention pin 115, alignment is maintained, simplifying the reinsertion step.

Abstract: A semiconductor device includes an elongated, blade-shaped semiconductor element isolated from a surrounding region of a semiconductor substrate by buried and side oxide layers. A polysilicon post disposed at one end of the element has a bottom portion extending through the buried oxide to contact the substrate, providing for electrical and thermal coupling between the element and the substrate and for gettering impurities during processing. A device fabrication process employs a selective silicon-on-insulator (SOI) technique including forming trenches in the substrate; passivating the upper portion of the element; and performing a long oxidation to create the buried oxide layer. A second oxidation is used to create an insulating oxide layer on the sidewalls of the semiconductor element, and polysilicon material is used to fill the trenches and to create the post.