Abstract: In a laser printer which uses a scanning mirror 12 with torsional hinges 36A, 36B driven by electrical coils 30A, 30B to provide resonant pivoting, at least one sensor 84, 88 is located proximate each end of a resonant sweep or scan. Pulses or signals from the sensor indicating the passing of a sweeping or scanning light beam are connected to computational circuitry 92 in a feedback loop. This information is used to determine the center of the beam sweep. The center of the beam sweep is then aligned with the center of the photosensitive medium, such as a rotating drum 44, by adjusting the DC current provided to the drive coils.

Abstract: A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0.32.

Abstract: A circuit for detecting a transmit diversity signal comprises a first circuit (706) arranged to receive a first synchronization code. The first synchronization code is modulated by a data signal. The first circuit produces a first output signal. A second circuit (732) is arranged to receive a plurality of predetermined signals. The second circuit produces a channel estimate. A detection circuit (710, 712) is arranged to receive the first output signal and the channel estimate. The detection circuit produces a signal corresponding to the data signal.

Abstract: Semiconductor devices and methods for making the same are described in which a single high k or ferroelectric dielectric layer is used to form decoupling capacitors and analog capacitor segments. Analog capacitors are formed by coupling analog capacitor segments in series with one another, wherein the capacitor segments may be connected in reverse polarity relationship to provide symmetrical performance characteristics for the analog capacitors.

Abstract: A method of forming a semiconductor component having a conductive line (24) and a silicide region (140) that crosses a trench (72). The method involves forming nitride sidewalls (130) to protect the stack during the silicidation process.

Abstract: A hybrid circuit has a transfer function having three zeros and four poles that are realized using only two fully-differential amplifiers in combination with a small plurality of resistors and capacitors, making the hybrid suitable for use with a communication medium comprising capacitively coupled non-ideal transformers and transmission lines while providing remarkably good hybrid rejection without the use of inductors.

Abstract: The present invention pertains to formation of a PMOS transistor wherein a layer of silicon or SiGe inhibits p-type dopant from entering into an underlying gate dielectric layer. The p-type dopant can be added to a gate electrode material that overlies the silicon or SiGe layer and can diffuse down toward the silicon or SiGe layer. The layer of silicon or SiGe may be formed to a thickness of about 5 to 120 nanometers and doped with a dopant, such as indium (In), for example, to deter the p-type dopant from passing through the silicon or SiGe layer. The dopant may have a peak concentration within the layer of silicon or SiGe near the interface of the silicon or SiGe layer with the underlying layer of gate dielectric material. Allowing the gate electrode to be doped with the p-type dopant (e.g., boron) facilitates forming the transistor with an associated work function having a desired value (e.g., coincident with a Fermi level of about 4.8 to about 5.6 electron volts).

Abstract: A process (111,101) of sending packets of real-time information at a sender (311) includes steps of initially generating at the sender the packets of real-time information with a source rate (s11) greater than zero kilobits per second, and a time or path or combined time/path diversity rate (d11), the amount of diversity (d11) initially being at least zero kilobits per second. The process sends the packets, thereby resulting in a quality of service QoS, and optionally obtains at the sender (311) a measure of the QoS. Rate/diversity adaptation decision may be performed at receiver (361′) instead. Another step compares the QoS with a threshold of acceptability (Th1), and when the QoS is on an unacceptable side of said threshold (Th1) increases the diversity rate (d11 to d22) and sends not only additional ones of the packets of real-time information but also sends diversity packets at the diversity rate as increased (d22).

Abstract: A Universal Serial Bus (USB) modem (14) in which reassembly and segmentation operations are performed outside of the host computer (12) is disclosed. A USB interface device (30) is coupled to a digital signal processor (DSP) (32) in the modem (14), and contains a shared memory (44) in which bulk endpoints (240) are established, at which ATM packet header and payload data are stored prior to transmission. An ATM transmit controller (132) retrieves the header portion of the ATM packet from a transmit endpoint (240) and stores the information in registers (252, 254, 256) in the ATM transmit controller (132). A four-byte ATM cell header is then transmitted to byte buffers (268) and to the DSP (32) for transmission over the communications facility. Afterwards, payload data is retrieved from the transmit endpoint (240) in shared memory (44), and forwarded to byte buffers (268) for transmission.

Abstract: An averaging circuit includes: input signal nodes for providing input signals 330; a multiplexing circuit 320 coupled to the input signal nodes for switching between the input signals 330 to create a time waveform; a low pass filter 300 coupled to an output 340 of the multiplexing circuit 320 for filtering the time waveform to create an average signal; and an average replication circuit 310 coupled to an output 350 of the low pass filter 300.

Abstract: A protection structure (30; 30′; 30″) for safely conducting charge from electrostatic discharge (ESD) at a terminal (IN) is disclosed. The protection structure (30; 30′; 30″) includes a pair of drain-extended metal-oxide-semiconductor (MOS) transistors (32, 34). In a pump transistors (32), the gate electrode (45) overlaps a portion of a well (42) in which the drain (44) is disposed, to provide a significant gate-to-drain capacitance. The drains of the transistors (32, 34) are connected together and to the terminal (IN), while the gates of the transistors (32, 34) are connected together. The source of one transistor (32) is connected to a guard ring (50), of the same conductivity type as the substrate (40) within which the channel region of the other transistors (34) is disposed.

Abstract: Ferroelectric materials useful in monolithic uncooled infrared imaging use Ca and Sn substitutions in PbTiO3 and also have alternatives with dopants such as Dy, Ho, Bi, Ce, and Fe. The ferroelectrics may also be used in non-volatile integrated circuit memories.

Abstract: A phase-locked loop (10) comprises a voltage-controlled oscillator (12) to which a control voltage is applied as produced by a phase/frequency detector (22) as a function of the difference between the frequency (fref) of a reference signal and the output frequency (fvco) of the voltage controlled oscillator (12) and the oscillator contains as a frequency-influencing circuit element a varactor (14) whose capacitance value can be varied over a fine adjustment range by the control voltage for altering the output frequency. A variable capacitance (18) is provided which can be connected in parallel to the varactor (14) when there is a change in the frequency (fref) of the reference signal, the value of this capacitance (18) being adjustable as a function of the control voltage output by the phase/frequency detector (22).

Abstract: A device and method for insuring the separation between a leadless chip carrier and printed wiring board, comprising aligning and attaching conductive pedestals to contact pads of either member and embedding the pedestals into the solder columns which are used to provide electrical connection. The conductive pedestals are comprised of an electrically conducting metal, solder, alloy or composite which will also provide thermal dissipation in selected designs.

Abstract: Methods and apparatus are disclosed for fabricating thick and thin gate oxide transistors in a semiconductor device, wherein lightly doped source/drain regions for the thick gate oxide transistors are formed using a threshold voltage adjust implant, and lightly doped source/drain regions for the thin gate oxide transistors are formed using an LDD implant. The use of threshold voltage implantation to form the lightly doped source/drain regions for the thick gate oxide transistors allows lower dopant concentrations therein compared with the thin gate oxide transistors without the need for separate LDD implantation processing for transistors of different gate oxide thicknesses.

Abstract: Disclosed are apparatus and method for limiting mobile charge (314) ingress within a silicon-on-insulator (SOI) substrate (300). A mask (308) is applied to the substrate to form an aperture (210) over a desired portion of the substrate near its outer edge. A buffer material (214), selected to impede mobile charge ingress, is implanted (310) through the aperture into the insulator layer (304) of the substrate to form a buffer structure (312).

Abstract: A TAP linking module provides for control and access of plural TAPs on an IC through one set of JTAG signal pins. The IC includes plural circuit modules, each with its own TAP, and boundary scan registers connected to an additional TAP. All the TAPs and the linking module have their TDI, TMS and TCK inputs connected to one set of input pins on the integrated circuit. The TDO outputs of all the TAPs and linking module are connected to the TDO pin through a multiplexer. A special instruction scanned into an enabled TAP produces a select signal to the linking module. This disables the enabled TAP and causes the linking module to be the scan path between the TDI and TDO pins. Selection data scanned into the linking module disables the linking module and enables a TAP to be connected between the TDI and TDO pins.

Abstract: A frequency bin method of carrier frequency acquisition uses a plurality of predetermined carrier frequency offset bins. A single bin is selected from among the plurality of bins. A local VCO is then adjusted to remove the carrier frequency offset associated with the single selected bin. Carrier frequency acquisition is then attempted using the adjusted VCO. If successful, the receiver enters its steady state operating mode. If unsuccessful, a new bin is selected and the VCO is again adjusted using the new carrier frequency offset associated with the newly selected bin. The process is repeated until successful communication is achieved in association with a properly adjusted VCO.

Abstract: The present invention comprises a low side reverse recovery sense circuit (401) and a high side reverse recovery sense circuit (601), of a low side over-current circuit of a power output stage (400) and a high side over-current of a power output stage (600), respectively, operable to sense current through said low side and high side primary circuit and accurately control said current when an over-current threshold is detected while disabling such circuit when a reverse recovery spike is detected.

Abstract: Variable sample rate converter by convolution of input data samples with an impulse response to produce output samples with the impulse response values generated by interpolation from a table of oversampled values with the oversampling rate lower for outlying lobes of the impulse response.