Abstract: A micro-electro-mechanical system (MEMS) resonant scanning mirror driver circuit has separate amplitude and waveshape inputs which allows a relatively slow and therefore inexpensive DAC to be used to control the amplitude of the drive signal for the MEMS device.

Abstract: A surface mounted power transistor is provided with a heat sink by positioning a mounting plate of a heat sink between the power transistor and a solder pad on the circuit board. The mounting plate of the heat sink is provided with a plurality of openings through which the solder of the solder pad flows during the solder reflow process so that the mounting plate is securely adhered between the power transistor and the circuit board. The mounting plate of the heat sink is connected thermally to an extension member which extends generally perpendicular to the mounting plate, the extension member in turn being connected to a heat dissipation surface which may be one or several fins.

Abstract: A DC—DC converter prevents reverse current from flowing through the inductor, suppresses ringing noise in the low-load state, lowers the power consumption, and increases the conversion efficiency. In the DC—DC converter composed of switches S1-S4 and inductor L1, in switching controller 10, output voltage Vout and current IL in inductor L1 are detected, and in accordance with the detection result, switches S1-S4 are turned on/off so that output voltage Vout is held at desired level; also, when the current in inductor L1 is nearly zero, switches S2 and S3 are turned on, and switch S4 on the output side of inductor L1 is turned off, so that reverse current flow through the inductor can be prevented, and the generation of ringing noise can be suppressed.

Abstract: A test cell (12) provides boundary scan testing in an integrated circuit (10). The test cell (12) comprises two memories, a flip-flop (24) and a latch (26), for storing test data. A first multiplexer (22) selectively connects one of a plurality of inputs to the flip-flop (24). The input of the latch (26) is connected to output of the flip-flop (24). The output of the latch (26) is connected to one input of a multiplexer (28), the second input to the multiplexer (28) being a data input (DIN) signal. A control bus (17) is provided for controlling the multiplexers (22, 28), flip-flop (24) and latch (26). The test cell allows input data to be observed and output data to be controlled simultaneously.

Abstract: An apparatus for use with a charge control system for affecting current draw from a charging unit coupled at an input locus of the charge control system for charging a battery unit includes a current sink switchingly coupled with the input locus for selectively contributing a predetermined current draw at the input locus. A method for selectively establishing a predetermined current draw from a charging unit coupled at an input locus with a charge control unit for charging a battery unit includes the steps of: (a) providing a current sink switchingly coupled with the input locus; (b) sensing at least one predetermined condition in the battery unit; and (c) switchingly engaging the current sink when the at least one predetermined condition satisfies at least one predetermined criteria.

Abstract: The present invention is a method and system for managing memory in a communication device which operates in a shared access media environment. In one aspect of the invention, each incoming broadcast frame of data has an associated reference mask to indicate through which of a number of channels the frame of data is to be transmitted.

Abstract: The present invention provides a method for determining resist trim times in an etch process. In one embodiment of the invention, the method for determining resist trim times includes obtaining resist profile data and critical dimension (CD) data of a patterned resist layer using a scatterometer, in a step 520, and then obtaining an estimated trim time of the patterned resist layer using the resist profile data and critical dimension data, in steps 530-550.

Abstract: A glitch free self-correcting clock switching mechanism operative to switch between two clocks in a glitch free manner while compensating for the ambiguity inherent in the switching operation. During the switching from fast to slow clock domains the mechanism measures the uncertainty or ambiguity of the first slow clock cycle duration during the switching operation and stores this value. At some time later, during the slow to fast clock switching the clock switch mechanism compensates for the metastability of the first slow clock cycle during fast to slow switching using the ambiguity value previously measured. In this manner the fast and slow clocks are switched between each other in a glitch-free and self compensating manner.

Abstract: A memory circuit and method for reducing gate oxide stress is disclosed. The circuit includes a memory cell for storing data. The memory cell has a first 106 and a second 110 control terminal and a pass transistor 102. The pass transistor has a control gate coupled to the first control terminal. The memory circuit includes a drive circuit 900 having an output terminal 912 coupled to the second control terminal. The drive circuit is arranged to produce a control signal PL having a rise time and a fall time, wherein the fall time is greater than the rise time.

Abstract: High-k transistor gate structures and fabrication methods therefor are provided, wherein a gate dielectric interface region near a semiconductor substrate is provided with very little or no nitrogen, while the bulk high-k dielectric is provided with a uniform nitrogen concentration.

Abstract: Methods are disclosed for forming ultra shallow junctions in semiconductor substrates using multiple ion implantation steps. The ion implantation steps include implantation of at least one electronically-active dopant as well as the implantation of at least two species effective at limiting junction broadening by channeling during dopant implantation and/or by thermal diffusion. Following dopant implantation, the electronically-active dopant is activated by thermal processing.

Abstract: An output stage provides increased current sourcing capability through a technique of local positive feedback. Current through a transistor MP2 is mirrored by the output current source IOUT that is desired to be increased. Without positive feedback, the gate of MN2 would be fixed by MP1 and MN1, and when input voltage VIN decreases by an incremental voltage &Dgr;V, the resulting current increase would distribute an increased voltage not only across MP2's VGS but also in the VGS of another transistor MN2; therefore, undesirably, not all of the &Dgr;V voltage change is mirrored in IOUT. However, if positive feedback such as MP5 is provided, the feedback dynamically increases the voltage at the gate of MN2. The increased voltage of MN2's gate essentially provides more voltage “headroom” for MP2 and MN2, and allows current through MP2 to increase with any voltage decrease in VIN.

Abstract: The present invention provides a method, system and apparatus for managing data flow over an open system interconnection type network (10) which includes a physical layer (12) and a media access control layer (146). The invention implements a plurality of operating modules (315) each enabling a respective media access control layer operating function in which at least a portion of the operating modules are implemented in software. The invention further implements a host interface module (305) for communication between a host processor and the media access control layer, a physical layer interface module (310) for communication between the physical layer and media access control layer, and an inter-module programming interface for communications between respective operating modules.

Abstract: A phase-domain digital PLL loop is implemented using a hybrid of predictive and closed-loop architecture that allows direct DCO oscillator transmit modulation in the GFSK modulation scheme of “BLUETOOTH” or GSM, as well as the chip phase modulation of the 802.11b or Wideband-CDMA. The current gain of the DCO oscillator is predicted by observing past phase error responses to previous DCO corrections. DCO control is then augmented with the “open-loop” instantaneous frequency jump estimate of the new frequency control word.

Abstract: An improved bond integrity test system is provided by eliminating the spring loaded wire spool cover which contributes to particulate matter, and by addition of a second contact diverter in the wire path. These improvements have been shown to decrease false lifted ball bond reports by 68%, and therefore to improve productivity and accuracy of the test system. Such changes are readily adapted to current bonders, as well as to new designs.

Abstract: A processing engine including a processor pipeline 820 with a number of pipeline stages, a number of resources and a pipeline protection mechanism. The pipeline protection mechanism includes, for each protected resource, interlock detection circuitry 1402 for anticipating and/or detecting access conflicts for that resource between the pipeline stages. An output of the interlock detection circuitry is connected to reservation and filtering circuitry 1404 for selection of a shadow register. If a shadow register is available, shadow management circuitry 1406 generates corresponding control signals 1410, 1412 to a set of shadow registers 1400. By writing into a selected register, a pipeline conflict is resolved. At a later cycle, a delayed write to a corresponding target register restores the pipeline. Conflicts that cannot be resolved are merged by merge circuitry 1440 to form stall control signals for controlling the selective stalling of the pipeline to avoid the resource access conflicts.

Abstract: An embodiment of the invention is a gate electrode 70 having a nitrided high work function metal alloy 170 and a low work function nitrided metal alloy 190. Another embodiment of the invention is a method of manufacturing a gate electrode 70 that includes forming and then patterning and etching a layer of high work function nitrided metal alloy 170, forming a layer of low work function nitrided metal alloy 190, and then patterning and etching layers 170 and 190.

Abstract: Plasma charging devices and methods are disclosed for detecting plasma charging during semiconductor wafer processing. Charging monitors are disclosed having ferroelectric capacitance elements which can be preprogrammed prior to processing steps of interest, and then subsequently measured afterwards, in order to determine whether plasma related charging is a problem in the intervening processing steps.

Abstract: Methods and apparatus are disclosed for selectively inducing stress in a semiconductor device, wherein a first region of a substrate is implanted so as to induce stress in a second region. An electrical device is formed at least partially in the second region, wherein the induced stress therein may improve one or more operational characteristics of the device, such as channel region carrier mobility.

Abstract: A batteryless transponder (10) which acquires its supply energy in that it rectifies an RF interrogation pulse transmitted by an interrogation device during a reception phase and that it uses the direct current so obtained to charge a storage device which serves as a supply voltage source during a transmission phase. In response to the reception of the RF interrogation pulse, the transponder transmits the information stored in it, wherein the coil of a tuned circuit serves as an antenna for both the reception of the interrogation pulse and the transmission of the information. The transponder contains a controllable switching device (14, 16, 18, 20, 22) which disconnects the tuned circuit (26) from the supply source during the transmission phase, and connects it to the supply voltage source only for a duration which is short as compared with a quarter period of the resonant oscillations, depending on the occurrence of each oscillation minimum of the resonant oscillations.