Abstract: An integrator circuit is connected to a capacitor that is to be measured and the capacitor driven by a read pulse. A first switch grounds the integrator input between read pulses and a second switch applies a bias input to the integrator. The bias is selected so that the integrator is active and its output high. Then, during the read pulse interval, the integrator will hold its input close to ground so that the capacitor to be measured will transfer a maximum charge to the integrator feedback capacitor. Additionally, the stray capacitance at the integrator input has little effect and the output will be a strong function of the value of the capacitor to be measured. The circuit has application in capacitor measurement and is useful as a ferroelectric memory preamplifier which acts to amplify the difference in capacitance produced by the polarization state of a ferroelectric memory capacitor. A CMOS preferred embodiment is disclosed in the form of a memory sense preamplifier.

Abstract: A transfer molded plastic package having a cavity for accommodating a semiconductor chip is disclosed. A leadframe assembly process is shown wherein the leadframe finger pattern is provided with a resilient or elastic O-ring bead. Top and bottom housing plates which have dimensions that are larger than the bead form the upper and lower surfaces of the package. These plates can be formed of any suitably rigid material. They may be composed of ceramic in low power devices. For high power operation at least one metal plate can be employed. The chip or chips are connected to the lead frame and, along with the top and bottom plates, is located in a transfer mold. The plates are in registy and located so that their outer edges extend beyond the O-ring bead. The mold cavities include faces which press against the plates which are held apart by the O-ring bead so that the bead is compressed by the mold closure.

Abstract: A plastic pin grid array package is detailed. Where the semiconductor device is mounted within a cavity in the printed wiring board, it is surrounded by a ring of holes that extend completely through the board. When the plastic housing is transfer molded around the face of the board, plastic will enter the holes thereby forming plastic pillars that lock the encapsulant to the board mechanically. When the package is flexed, the pillars will prevent any motion between the encapsulant and the board or the semiconductor device mounted thereupon. The invention can be applied to single or multichip packages. It can be employed in any package that is based upon a printed wiring board substrate.

Abstract: A process for forming an IC isolation trench pattern wherein the trenches have varying widths and are filled with near intrinsic single crystal silicon. Thus, the wiring that passes over the trenches has low capacitance and active circuit devices having improved high frequency performance can be fabricated into the silicon in the trenches. This increases the utilization of surface area thereby increasing active device density for VLSI applications.

Abstract: In a semiconductor device tape assembly bonding process the fingers of a copper tape are reflow soldered to metal bumps located on the semiconductor device. First, the semiconductor wafer is covered with a conductive film composed of thin layers of aluminum, nickel-vanadium alloy and gold. The bumps are then created by electroplating gold through openings in a photoresist mask. The gold bumps are overcoated with a contolled thickness tin layer and the tin is overcoated with a thin gold anticorrosion layer. The copper assembly tape is coated with a thin gold layer and are lightly pressed against the bumps by means of a thermode. The thermode is quickly heated to a temperature well above the gold-tin eutectic melting temperature and then rapidly cooled. The tin layer on the bump will combine with the adjacent gold to form a liquid phase eutectic which will form and contact both the copper finger and the gold bump. Upon cooling the eutectic melt will solder the finger to the bump.

Abstract: Operational amplifiers are often used in unity gain configurations where the output is fed back to the input. In the noninverting buffer configuration the output is directly connected to the inverting input and the circuit becomes a voltage follower. In many cases, the input stage includes cascode coupled transistors which isolate the current mirror load from the differentially operated input transistors. Such cascode transistors act to increase gain to reduce noise and to increase the power supply rejection ratio. When cascode coupled transistors are employed the frequency compensation capacitor can be isolated from loading effects on the input stage, thus, further enhancing the value of a cascoded input stage. However, when such an operational amplifier is operated as a unity gain device its transient response can suffer. Negative output transitions can result in circuit ringing following the negative output transient steps.

Abstract: A process is disclosed for controlling the diffusion of aluminum in silicon for the fabrication of monolithic pn junction isolated integrated circuits. Germanium is incorporated into the silicon where isolation or p-well diffusion of aluminum is to occur. Aluminum diffusion is modified by the presence of the germanium so that channeling and out diffusion are controlled. The control is enhanced when boron is incorporated into the silicon along with the aluminum.

Abstract: An integrated circuit which will produce a switched output when the circuit power supply drops a predetermined level below which reliable IC operation is not assured. This reduced power supply condition is referred to as brownout wherein the switching is related to the active devices. A preferred CMOS circuit is disclosed. The switching level is related to the N channel and P channel transistor sum of thresholds which makes the CMOS circuit process adaptive. The circuit is provided with a transistor gate oxide capacitor for improving noise immunity while achieving maximum utilization of IC chip area. In addition, output enable and circuit shutdown capabilities are detailed.

Abstract: A transfer molded plastic package having a cavity for accommodating a semiconductor chip is disclosed. A leadframe assembly process is shown wherein the leadframe finger pattern is provided with a resilient or elastic O-ring bead. Top and bottom housing plates which have dimensions that are larger than the bead form the upper and lower surfaces of the package. These plates can be formed of any suitably rigid material. They may be composed of ceramic in low power devices. For high power operation at least one metal plate can be employed. The chip or chips are connected to the lead frame and, along with the top and bottom plates, is located in a transfer mold. The plates are in registy and located so that their outer edges extend beyond the O-ring bead. The mold cavities include faces which press against the plates which are held apart by the O-ring bead so that the bead is compressed by the mold closure.

Abstract: A sample and hold circuit is disclosed in which differentially coupled input stages are multiplexed to drive a common output stage. In this way, a plurality of input stages can be employed wherein the transition between sample and hold modes produces greatly reduced switching transients. The circuit has very high overall gain so that sampling accuracy is improved and a very low current input stage configuration permits the use of small hold capacitors without introducing excessive droop in the hold mode. The differential balance is completed by a dummy hold capacitor which is switched along with the hold capacitor. Both of these capacitors are switched in a virtual ground configuration.

Abstract: In an integrated circuit a PNP current mirror can lose its current reflection accuracy when low Beta transistors are involved. Since the conventional PNP transistors can often have low Beta this can become a serious problem particularly with high current gain plural output current mirrors. In the invention a compensation current is fed to the current mirror to increase the PNP transistor base currents as an inverse function of Beta. Several alternative circuit embodiments are also disclosed.

Abstract: A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.

Abstract: A P-type buried layer is described for use with planar, silicon, monolithic, epitaxial, PN junction-isolated transistors of PNP conductivity primarily for use in IC construction. The buried layer includes a high concentration of boron and gallium along with germanium, which is in sufficient concentration to inhibit impurity diffusion in the silicon epitaxial layer. This inhibition effect has been found to be sufficient to cause the combination of boron and gallium to act as slow diffusers. The result is that the performance of arsenic and antimony, in the creation of buried layers for NPN transistors. Thus, the performance of NPN transistors can be matched for PNP transistors. This means that an IC can be fabricated so that more nearly equal performance NPN and PNP transistors can be fabricated simultaneously in a common substrate.

Abstract: Integrated circuit bonding pads are sealed by a surface passivation coating. The bonding pads are first edge-sealed by means of a first applied passivation coating that overlaps the edges of the bonding pad while leaving the central area uncoated. Then, a sequence of metal layers applied to overlap the open central area of the bonding pad. The layer sequence includes an optional first adherence layer such as aluminum, a barrier metal layer such as titanium-tungsten alloy, and an outer noble metal layer such as gold. Then, a second passivation layer is applied so as to overlap and seal the edges of the sequence of metal layers so as to leave only the central portion of the noble metal layer exposed. Electrical contact to the IC is then made to the exposed noble metal in the conventional manner. With respect to the passivating coatings, either or both can be silicon dioxide overcoated with silicon nitride.

Abstract: A process for creating self-aligned vertically arrayed planar transistors. The preferred embodiment relates to the simultaneous fabrication of both NPN and PNP planar vertically arrayed transistors in a conventional monolithic, epitaxial, PN junction isolated, integrated circuit. A field oxide is employed to surface isolate the devices and assist in the self-alignment improvement.

Abstract: An integrated circuit is shown in which provision is made for terminating or locking out the operating circuitry when the supply voltage has fallen below a level that can cause anomalous or unreliable operation. Certain selected transistors are provided with saturation sensors which operate to produce a current when the transistors go into collector saturation. When any of the sensors indicates the onset of saturation, clamping circuitry is energized to provide lock out. In addition, a temperature compensated dummy bandgap circuit is included to sense extremely low supply voltages and provide the lockout function under conditions where a reliable saturation indication might not be available.

Abstract: An RGB video display terminal (VDT) is disclosed and the color cathode ray tube (CRT) driver circuits detailed. The driver circuits include a common video gain control which can be varied over a wide range without changing the DC bias level. Each CRT gun can have its driver gain separately controlled over a vernier range and its DC bias can be separately controlled. The video amplifier is AC coupled to the video input and includes a DC reinsertion circuit which clamps the DC bias at a level related to the composite video level immediately following the sync pulse. Therefore, the DC reinsertion is clamped for each scanning line at the CRT black level. The video amplifier also includes a blanking circuit which turns the CRT guns off during the VDT retrace interval. Thus, the driver circuits can drive the CRT guns in a manner that will simultaneously control their operation for the color display and yet take into account the manufacturing tolerance in individual gun characteristics.

Abstract: A method and structure for performing data synchronization by delaying the input data for substantially one-half of the VCO signal period and then comparing the phase of the delayed input data to the VCO signal. The phase difference is filtered and controls the frequency of the VCO signal to align the VCO signal with the delayed input data. The delayed input data is clocked into a flip-flop on the opposite phase of the VCO signal to produce an output signal. In a preferred embodiment the delay of the input data for phase comparison, and the delay of the input data for the output flip-flop can be independently selected.

Abstract: A CMOS switch driver capable of driving a plurality of CMOS switches is disclosed. A pair of cascade coupled output inverters provide the complementary driver outputs. Their inputs are obtained respectively from the first of the pair and a third, or input, inverter. The circuit includes resistance elements in the output inverters that greatly reduce current spikes.

Abstract: A circuit capable of being integrated into a self-isolated DMOST is driven by a sense resistor that is created from the DMOST drain metallization. The circuit produces an output current that is ratioed with respect to the DMOST current with the ratio being determined by the value of a single resistor. The output current is sourced when the DMOST conducts its source current and the output current is sunk when the DMOST shunt diode conducts. Thus, the circuit not only produces a DMOST current related output it also distinguishes the mode of DMOST conduction.