Abstract: A process is disclosed for forming an oxide isolated semiconductor wafer which can include the formation of an associated high voltage transistor. The same wafer can include a plurality of low voltage transistors which can be connected in the form of circuitry that can control the high voltage transistor. Thus, a single IC chip can be fabricated for a power control function. The process includes bonding a first wafer to a second wafer using oxide (11/14), forming a groove (18) through the oxide (15), backfilling with epitaxially regrown semiconductor (19) to provide a high voltage section, and subsequently forming the high voltage transistor, e.g. NPN or DMOS devices, in said section.

Abstract: A low dropout voltage regulator with quiescent current reduction has a pass transistor coupled for conduction from a positive supply terminal to a regulated output terminal. A first switch is coupled to conduct the base current of the pass transistor to the regulated output terminal. A second switch is coupled to conduct the base current of the pass transistor to ground. A control circuit selects the action of the switches to select the conduction path for base current.

Abstract: An integrated circuit is disclosed having a thermal shutdown capability. A single chip bonding pad is coupled to a circuit that will operate the bonding pad at a low potential for normal conditions and will pull it high when a temperature threshold is crossed. Thus, the normally low bonding pad provides a temperature flag. The bonding pad is also coupled to a latch that will hold it high and to a lockout circuit that acts to disable the heat producing chip circuitry. Therefore, when the bonding pad is once driven high the circuits are locked out and will remain out until a start up command is present. This is achieved by either momentarily removing the power supply or by pulling the bonding pad low. Both manual and computer control of the circuit is disclosed.

Abstract: A CMOS relaxation oscillator is disclosed employing a pair of capacitors and individual charging means. A noninverting amplifier comprising two cascaded inverters is provided with a transmission gate input circuit that alternately switches the amplifier input between the two capacitors. A pair of switches coupled respectively across the capacitors alternately discharge them. The resulting oscillator has a frequency determined by the capacitor charging periods. Accordingly, the frequency and duty cycle can be predetermined as desired. The circuit can also be made either power supply tunable or power supply independent.

Abstract: A CMOS structure is employed to create an isolated large area power output transistor along with a voltage multiplier that acts to develop an overdrive bias in response to clock pulses. The circuit can be employed to couple a relatively low power supply voltage to an output terminal while encountering a small voltage drop across the power transistor.

Abstract: A voltage controlled oscillator includes an emitter coupled multivibrator in which a capacitor determines the frequency of oscillation along with a pair of load resistors and a pair of current sources. A differential amplifier is coupled to operate in parallel with the mutlivibrator and its tail current is operated differentially, with respect to the currents in the pair of sources, in response to the input voltage at a first modulation input port. Thus, a constant current flows in the multivibrator loads even when the frequency is modulated. A second input port is coupled to vary the tail current in the differential amplifier to comprise a dual port control of the voltage controlled oscillator. The circuit can be operated at a relatively low supply voltage and can be temperature compensated. Furthermore, the input ports can include circuitry having a logarithmic response for digital signaling processing.

Abstract: A molded pin-grid-array package includes a heat sink available at the face opposite to the pins. The heat sink is secured to a printed wiring board that has plated through holes therein that form the desired pin-grip-array and wires are secured in the holes to form the package pins. The heat sink covers an aperture in the board and the semiconductor die is secured to the heat sink inside the cavity thereby formed. After the semiconductor die is attached and the bonding pads connected to the metal traces on the board, the assembly is placed in a transfer mold. Plastic encapsulant is then transfer molded to encapsulate the semiconductor die and to extend flush with the heat sink to form a skirt around the periphery of the board. This leaves the molded package with an available heat sink face for efficient cooling after the package is mounted for ultimate use.

Abstract: A sidebrazed ceramic package is provided with a closure seal that employs a high alumina ceramic lid that matches the composition of the package body. The lid is provided with a recess in the sealing face and the sealing face is provided with metallization that adheres to the ceramic and is wet by solder. The metallized ceramic lid is sealed to the metallization ring on the sidebrazed ceramic body by means of the conventional gold-tin solder. The resultant hermetic seal can be inspected by observing the solder fillet in the lid recess. Such a closure seal is fully hermetic and can readily survive repeated thermal cycling.

Abstract: A PRIMOS (Planar Recessed Isolated MOS) transistor and a method for fabricating same is described wherein the source and drain in a semiconductor body are separated by a recess. A gate oxide is disposed on the body in the recess, with conductive gate material thereon. Oxide regions are positioned on each side of the gate, such oxide regions being substantially thicker in cross-section than the gate oxide. The method described teaches fabrication of this device.

Abstract: A circuit and structure intended for use in CMOS IC designs acts to protect signal lines against ESD. An array of three transistors is connected so that the voltage pulse that appears on the signal line as a result of ESD, forces at least one transistor into conduction. The circuit responds equally to positive and negative pulses and is, therefore, symmetrical, and independent of bias or supply potentials. In the absence of an ESD pulse the circuit draws a very low leakage current and, therefore, has very little effect upon normal IC operation.

Abstract: A phase detector and charge pump combination is disclosed for use in a digital phase locked loop system. The phase detector includes a reset circuit that responds to the charge pump condition where it is simultaneously sourcing and sinking current. The pump up and down circuits are fast acting and balanced so that minimum conduction is employed for the phase lock condition.

Abstract: An improved copper bump tape for tape automated bonding inhibits electromigration of the copper after bonding to a semiconductor device. The improved tape is characterized by the plating of a migration resistant metal onto the inner ends of connector beams of the tape. The migration resistant metal is coated onto all surfaces of the connector bump, except for the surface which is to be bonded to the semiconductor device. In this way, the surfaces of the bump which remain exposed after connection to the semiconductor are inhibited from electromigration.

Abstract: A soft start circuit for a switching regulator is disclosed. The circuit does not require any off-chip parts and, therefore, a five-pin package can be employed. The operation of a soft start circuit in conjunction with a switching regulator operating in the voltage boost mode is set forth in detail.

Abstract: A switched capacitor amplifier circuit using a pair of switched capacitors to replace each resistor element of an inverting operational amplifier circuit, with the capacitors operating on opposite halves of the switching cycle to provide reduced sampling distortion.

Abstract: In a monolithic silicon integrated circuit fast diffusing impurities are incorporated into the collectors of the bipolar lateral transistors. The impurity level is controlled, using ion implantation, so that after device processing the lateral transistor collectors extend an additional increment into the base. This increment is doped with the fast diffusing impurity at a level that overcompensates the normal base impurity to the opposite conductivity type and conductivity about equal to that of the base. Thus the collector junction is moved towards the emitter and is symmetrical in terms of conductivity. This means that when the collector is reverse biased the depletion field extends about equally on both sides of the junction. This action greatly relieves the voltage gradient and stress so that collector junction voltage breakdown is enhanced. Since the collector junction is closer to the emitter the transistor current gain and frequency response are enhanced.

Abstract: A pair of voltage triplers are formed in a C/DMOS circuit along with a self-isolated DMOS transistor. The voltage triplers are driven in phase opposition from the system clock and their outputs commonly drive the gate of the DMOS transistor which acts as the pass element in a voltage regulator. A control circuit includes a reference voltage generator and a differential amplifier that senses a fraction of the d-c output voltage. The amplifier has an output coupled to the DMOS gate thereby to create a stabilizing negative feedback loop. The voltage triplers overdrive the DMOS transistor so the dropout voltage is low and the full wave rectifier action will double the clock frequency for easier filtering.

Abstract: An encapsulated die package (20) is shown in which a semiconductor die is connected in a die-attach aperture of a copper foil tape (11). Die contact pads (31) are bonded to the inner ends (31a) of interconnected finger contacts (13) on the tape. Finger contacts etched in the foil include splayed out portions (15) extending to probe ends (19). Interconnect cross-links (16) initially connect the finger contacts and the tape edges and function as dam bars in subsequent encapsulation steps. The die and die bonds are mold encapsulated to form the die package (20) and a carrier frame (17) is simultaneously molded around and spaced from the periphery of package (20). The probe ends are exposed within a slot (34) in the frame or extend from the ends of the frame so that probe tips can be pressed thereon to test the die and its bonds. Prior to testing, the interconnects exposed in the annulus between the package and the carrier are blanked out so that each finger leading from a die contact pad becomes discrete, i.e.

Abstract: The copper tape that is used in the tape assembly of semiconductor devices is provided with a bondable surface by an electroplated layer of copper. The copper tape is passivated in a weak organic acid solution immediately after plating. In the preferred embodiment the copper tape is also cleaned and passivated prior to electroplating. The passivated copper can be thermosonically bonded using gold wires for up to 144 hours after preparation. The elimination of noble metal plating reduces assembly cost and the passivated copper bonds well to the subsequently applied plastic encapsulant.

Abstract: A feed mechanism for a tape applying machine in the semiconductor lead frame arts, especially suitable for discrete pieces of lead frame, in which pins are inserted into holes in the lead frame and advanced periodically. The pins are deliberately made smaller than the holes and moved in such a way as to always return to the center of the holes, well clear of the edges, before entering or withdrawing from the holes.

Abstract: A shipping tray that can be adjusted to various internal dimensions, by different placement of one or more moveable partitions. The partitions are held in position by means of interlocking surfaces formed on the ends and bottom of the partition and on the inside walls and interior bottom of the tray.