Abstract: A circuit for producing a programmable phase shift of clock pulses in response to the data on a group of control lines. The circuit includes a ramp generator stage coupled to drive a comparator stage which has a reference potential input determined by the control line data. The phase shift can be employed to produce a series of subnanosecond delay increments on the clock pulses and is useful in the fine adjustment of a digital phase lock loop.

Abstract: An improved copper bump tape for tape automated bonding inhibits electromigration of the copper after bonding to a semiconductor device. The improved tape is characterized by the plating of a migration resistant metal onto the inner ends of connector beams of the tape. The migration resistant metal is coated onto all surfaces of the connector bump, except for the surface which is to be bonded to the semiconductor device. In this way, the surfaces of the bump which remain exposed after connection to the semiconductor are inhibited from electromigration.

Abstract: A tachometer circuit is described that has a zero ripple d-c output that is directly proportional to the frequency. The circuit includes a pair of full wave rectifiers to act upon the sine and cosine signal inputs. The rectified currents are first squared, then summed together and finally the square root is taken. Since the quantity .sqroot.sine.sup.2 +cosine.sup.2 is a constant, there is no ripple and no output filtering is required to eliminate ripple. This means that the output can follow very rapid changes in frequency and no lag is introduced by the inclusion of low pass signal filtering.

Abstract: A threshold detector circuit and method for providing an output signal indicative of the relative magnitude of an input signal and a predetermined threshold value. The circuit, which is powered by the input signal and does not require a separate power source, includes a reference stage which switches from one state to another state when the input to the reference exceeds a predetermined reference voltage. The reference voltage is equal to the sum of two voltages having positive and negative temperature coefficients, respectively so that the total coefficient is small. A pair of transistors operating at different emitter current densities provide a difference in base-to-emitter voltages used to derive the first voltage and an absolute base-to-emitter voltage is used for the second voltage. An input stage is included which has a transistor for coupling the detector input to the reference stage input.

Abstract: An integrated circuit voltage follower buffer amplifier is provided with a feedback capacitor that is coupled to produce positive feedback current that acts to enhance slew rate. In an op amp a polarity sensitive slew rate enhancement acts to correct slew rate asymmetry. Circuits are shown for avoiding assymetry or boosting slew rate of both polarities. In all cases, the positive feedback current is made proportional to the rate of change of the output voltage.

Abstract: An encapsulated die package (20) is shown in which a semiconductor die is connected in a die-attach aperture of a copper foil tape (11). Die contact pads (31) are bonded to the inner ends (31a) of interconnected finger contacts (13) on the tape. Finger contacts etched in the foil include splayed out portions (15) extending to probe ends (19). Interconnect cross-links (16) initially connect the finger contacts and the tape edges and function as dam bars in subsequent encapsulation steps. The die and die bonds are mold encapsulated to form the die package (20) and a carrier frame (17) is simultaneously molded around and spaced from the periphery of package (20). The probe ends are exposed within a slot (34) in the frame or extend from the ends of the frame so that probe tips can be pressed thereon to test the die and its bonds. Prior to testing, the interconnects exposed in the annulus between the package and the carrier are blanked out so that each finger leading from a die contact pad becomes discrete, i.e.

Abstract: A power switching circuit 12 for automatically switching between line-driven and battery power supplies 28 and 30 is disclosed. The power switching circuit selectively connects first and second input voltage terminals Vdd and Vbb to an output voltage terminal Vzz. When the line-driven power supply is on, a first transistor Q1 switches on to connect the first input voltage terminal to the output voltage terminal, and a second transistor Q2 switches off to isolate the battery. When the line-driven power supply is off, the first transistor switches off, and the second switches on to connect the battery powered second input voltage terminal to the output voltage terminal.

Abstract: A digital bus backplane is disclosed that has interface circuitry located on the backplane. The backplane includes a backplane circuit board containing signal bus lines each operable for conducting electrical signals, several connectors each physically coupled to the backplane circuit board and each operable for electrically contacting the signal pins of a daughter board inserted into the connector, and many transceivers each physically coupled to the backplane circuit board and each electrically connected between one of the contact pins of a connector and one of the signal bus lines, where each transceiver is operable for relaying electrical signals between a daughter board and a signal bus line.

Abstract: A bipolar switch is disclosed having a near zero standby current characteristic, low output impedance in the "on" state, and near infinite impedance in the "off" state. The switch is responsive to a control signal to apply regulated power to a load. The switch includes a turn-on detect circuit which is powered solely from the control signal, and switching circuitry which is powered from a power source but which normally draws no standby current when the switch is in its "off" state. The switching circuitry includes speed-up circuitry to permit rapid turn-on, circuitry which employs positive feedback to achieve high current gain, and circuitry for rapidly turning off the switch.

Abstract: A pin-grid package is created by starting with printed wiring boards that have plated through holes that can accommodate wire pins. Pins are secured in position to extend outward from one face of the PW board in the form of a pin grid array of the desired configuration which is typically a plurality of concentric rings thereby creating a square grid pattern of predetermined spacing. The opposing PW board face includes a central pin-free area to which is secured a semiconductor die. This face of the PW board includes a plurality of wiring traces that connect each pin to an array that surrounds the semiconductor die. The traces are connected to the bonding pads of the semiconductor die by either wire bonds or a spider assembly using tape assembly bonding. The PW board is located in a mold that has a flat faced first platen that contains cut-out regions that will accommodate the package pins.

Abstract: An improved metal tape for tape automated bonding provides for enhanced heat dissipation from the packaged semiconductor device. The invention includes two aspects. In the first aspect, individual metal tape leads are extended inward beyond the peripheral bonding pads of the semiconductor and over the active region of the semiconductor device. In this way, the leads are able to conduct heat away from the active region of the device. The second aspect of the invention relates to improved heat dissipation through the individual leads. The leads are flared or otherwise increased in area in the direction away from the active region of the semiconductor device to prove the radiative dissipation.

Abstract: A metal housing is provided with lead in members by way of a compression seal using a glass that can be worked below about 480.degree. C. The housing and lead in members can be preplated in a low cost process to provide a suitable protective coating that is present under the glass after the seal is made. This obviates a post seal plating and therefore avoids the related problems. It also permits using aluminum as the housing material.

Abstract: A subsurface zener diode is formed in an N type semiconductor substrate such as the kind employed in the epitaxial layer found in silicon monolithic PN junction isolated integrated circuits. A P+ anode is ion implanted into and diffused from an oxide source and an N++ cathode is diffused within the confines of the anode. The cathode is surrounded with a counter-doped region that forces the PN junction breakdown subsurface. The resulting diode has a clean, sharp breakdown curve and the breakdown voltage can be tailored by controlling the anode deposition.

Abstract: A thermal shutdown circuit for use with a high power transistor which incorporates a sense emitter. A differential amplifier is driven from the transistor base and the sense emitter and has an output that is coupled to the power transistor base. When the sense emitter potential exceeds the base potential, the amplifier output will pull the base down so as to limit the current in the power transistor. For a silicon transistor, the circuit will act to limit the hottest portion of the sense emitter to a maximum of about 250.degree. C. When there are no hot spots and the sense emitter is heated uniformly, heating of the transistor will be limited to about 200.degree. C.

Abstract: An IC thermal shutdown circuit is based upon the thermal characteristics of a reverse biased PN junction diode. The leakage current, at bias levels below breakdown, is closely related to the high temperature IC performance limit. A hysteresis introducing circuit produces reliable switching at predetermined levels to shut down the IC when the maximum temperature limit is reached.

Abstract: A method and structure is provided for powering down a plurality of clocks in a predetermined sequence. In one embodiment, a clock is powered down when it reaches a predefined logical level following the receipt of a power down signal. In another embodiment, a clock is powered down in response to a power down signal when the clock reaches a predefined level, and all clocks derived from that clock reach predefined levels. This is accomplished by including an edge sense circuit for determining when a clock reaches a predefined level, circuitry for combining a plurality of logical signals which indicate when the clock has reached said predefined level, and when all clocks derived from that clock have been powered down. Means and structure are also provided for powering down internal read/write control signals in response to a power down signal, thereby minimizing power consumption which would occur if the read/write control signals were switching during the power down cycle.

Abstract: A circuit is described for trimming a monolithic PN junction isolated silicon IC. The value of a moderate value resistance network is translated to a current that can be made to have a predetermined temperature coefficient and can be applied to the IC. A voltage regulator is shown in which the output voltage and the temperature coefficient can be independently adjusted both at wafer sort and after assembly.

Abstract: A CMOS buffer is disclosed having a reference potential that provide TTL logic response. The circuit is configured to draw substantially zero current. A reference potential generator develops a potential that is one N channel transistor threshold above about 1.2 volts for TTL compatibility. A single reference potential generator will provide a potential for a plurality of buffers so that its dissipation is low and is shared among the buffers. The result is a low power buffer circuit that is compensated for variations in supply voltage, temperature and device parameters.

Abstract: A power transistor structure that is well suited to both switching and lower-voltage linear applications is displayed. A key element of the design is thin-film ballast resistors that act as a second level of interconnect. They can be connected to or insulated from the overlying metal and the underlying silicon, except where contact holes are provided. Thus, an intricate structure having small emitters with individual ballast resistors can be fabricated below the wide metal busses required to carry current out of a large power array. The result is a ballasting scheme that can be optimized for a wide range of linear and switching applications while making efficient use of metallization which often limits the size of power arrays. This is especially important in the design of IC power transistors where both the emitter and collector current must be conducted out of the array with surface metallization.

Abstract: Each cell of a static latch implemented in MOS transistor circuitry includes an MOS transistor configured to operate a depletion mode and operably coupled to communicate an output node of the cell to an input node of the cell in absence of a control signal, to effect the latching operation. Presence of the control signal allows data to be efficiently written to the cell by enabling a transfer gate to establish a communication path for the data to the input node of the cell, while at the same time disabling the MOS transistor to terminate communication of the output node of the cell to its input node during the write operation.