Abstract: Means are described for generating a pair of oscillator signals that will respectively drive P and N channel transistors in Class B. These signals are used to clock a synchronous inverter stage that will only change state during the appropriate time interval. Pairs of such stages are cascaded using common clocking to create a shift register which drives an output inverter, the output of which is coupled back to the input of the register. The output stage also has series-coupled P and N-channel transistor pairs for each pair of clocked inverters. Each transistor pair has its gates driven by the respective pair of clocked inverters. The output stage switches at a frequency which is a submultiple of the oscillator frequency, with the submultiple being equal to the number of inverters minus one. Since the inverters are fully Class B there is no direct current conduction due to simultaneous transistor conduction.

Abstract: A semiconductor device wherein surface stabilization is provided by a shallow layer of ion implanted doping material on the surface of the semiconductor and beneath the passivating oxide layer. One embodiment is a bipolar transistor including a collector region, a base region and an emitter region, the base region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a zener diode device with an anode region and a cathode region, the cathode region being provided with the shallow ion implanted layer at the surface thereof. Another embodiment is a JFET with a gate region and a source and drain region and a channel region extending through the gate region between the source and drain regions, the channel region being provided with the shallow ion implanted layer at the surface thereof.

Abstract: An indexing system adapted to periodically advance a web of metal through a plating line that first advances gently till it engages a hole in the web, then closes clamping members about the web to grasp the web over a distributed region, and only then moves the web at full speed.

Abstract: A partial silicide layer under a polycrystalline silicon (polysi) first level interconnect reduces the sheet resistance of the first level interconnect. The polysi insulates the silicide from possibly reactive materials and gases. Since the silicide is not deposited over contacts between the polysi and the substrate, conventional polysi/silicon ohmic contacts can be made.

Abstract: In an AM stereo radio receiver a filter is coupled to the IF amplifier and is tuned to the IF carrier frequency. The filter will ring at the IF and, if desired, can be incorporated into an oscillator circuit. The resulting signal acts as a reinserted carrier that will persist over those intervals during which the carrier would ordinarily be absent due to amplitude overmodulation. In effect the oscillatory signal sets the minimum value to which the carrier can be driven and will act to prevent the noise bursts that ordinarily accompany excessive modulation. Such overmodulation can result from inadvertence at the transmitter or from multipath reception.

Abstract: An interface circuit for converting a digital signal representing a dot-by-dot color video signal into a NTSC signal compatible with a television antenna input precompensates the digital for limitations in typical NTSC receivers. Various methods and circuits for precompensating the luminance amplitude, chrominance and chrominance amplitude content of the digital signal result in perceivably improved contrast and color purity.

Abstract: A contact for making electrical connections to a moving strip of metal, so as to permit plating the strip, in which grooved members engage just the edges of the strip, thus avoiding scratches on the face of the strip.

Abstract: A bubble sense amplifier has a biasing circuit for adjusting the bias currents through magneto-resistive detectors so as to establish a preferred common mode operating voltage across the bubble detectors. The preamplifier is coupled through a junction capacitance circuit to a clamp-and-strobe circuit and to a differential comparator. The differential comparator has a selectable threshold voltage, and compares the differential bubble signal to the selected threshold voltage.

Abstract: A two transistor CMOS inverter has the two transistor gates coupled together by a coupling capacitor. D-C gate bias is supplied to each transistor through high value resistors. The P-channel transistor is biased one threshold below V.sub.DD and the N-channel transistor is biased one threshold above ground. The biasing voltages are developed through the use of a current mirror so that the biasing is independent of processing variables and temperature. This form of biasing renders the circuit class B regardless of the source to drain voltage and ensures low current operation. A crystal oscillator created using such an inverter and biasing will operate at voltages substantially below sum of P and N thresholds and at a current level about one-fifth of that of a conventional CMOS oscillator.

Abstract: A MOS two-phase boostrap driver circuit, having a bootstrap transistor with a gate selectively charged or discharged in response to the level of an input signal, provides for selectively charging the gate of the bootstrap transistor directly from a voltage supply.

Abstract: In an AM stereo radio receiver, a pilot signal is recovered from the phase modulated channel. The pilot signal is sensed by means of a bandpass filter tuned to the subaudible signal frequency and is used to operate a detector-switching amplifier combination. The switching amplifier actuates a visual indicator which shows the presence of a stereo broadcast. The receiver is provided with an electronic blend function that operates in response to the pilot signal and an excess phase signal that is present when the receiver is mistuned. OR Logic, which responds to either mistuning or a lack of stereo pilot signal, switches the receiver to monaural response. If desired, further OR Logic can include response to weak signals, in which case an improvement in signal to noise ratio is achieved.

Abstract: A pair of common base connected transistors have their emitters coupled to provide the input terminals of a differential amplifier. The collectors are coupled to a current mirror that provides a small current bias that operates the transistors at equal current densities. The common bases are coupled to a node that is driven to a level that causes the bases to track the emitters with a one V.sub.BE offset that will therefore automatically adjust to conform to the applied current. When a remotely grounded transducer is coupled to the amplifier input it can operate at a common mode potential outside of the span of the power supply that operates the amplifier.

Abstract: A consumable-anode selective plating apparatus for plating a continuous metal strip having a container for containing a consumable anode material, a mask assembly for exposing selected areas of said continuous metal strip to an electrolyte, a source of electrolyte and a source of power and conductors for passing a current through said electrolyte, consumable anode material and metal strip.

Abstract: A content-addressable memory (CAM) has an array of four-transistor memory cells arranged in rows corresponding to stored words and columns corresponding to a selected search word. Complementary column lines couple signals associated with the bits of the search word to the memory cells associated with all of the stored words in parallel. The memory cells of each row are coupled to a common sense line and cause a current to flow on the sense line in response to the search word not matching the data word associated with that row.Writing is accomplished by discharging one of the sense lines and applying signals representative of the desired word to be stored to the column lines. Since the ground lines are not unique to any row, they can be shared between adjacent rows or columns as best suits the layout of the circuit.A status bit is associated with each stored word and is used to selectively activate the sense amplifier associated with each row.

Abstract: In an FM receiver a multiplier is driven from the IF limiter. The limiter also drives a single tuned circuit which produces a quadrature signal that drives a second port in the multiplier. When the quadrature signal is multiplied by the IF signal an FM detector results. The center frequency is determined by the frequency of the quadrature relationship and the extent of the resultant output curve is determined by the Q of the tuned circuit. The output response is linearized by varying the current in the multiplier as a function of the IF signal deviation.

Abstract: In AM radio receivers it is desirable to operate the automatic gain control so that strong signals are actually heard louder than weaker signals. This means that when AM stereo is incorporated into the radio, using a limiter and phase demodulator to recover the L-R stereo information, some means must be provided to cope with the variable L+R signal level. Typically this is done by using a gain control characteristic that eliminates the desired variable sound level. In the invention an absolute value detector is employed as an AM demodulator, the d-c output of which is related to the L+R signal content. A multiplier is coupled between the phase demodulator L-R output and the matrix in which the L+R and L-R signals are combined to produce the separate L and R signals. The multiplier is biased by the d-c component at the AM detector. Thus, as the L+R level varies, the L-R out of multiplier is varied to match.

Abstract: A process for fabricating JFET devices into a conventional CMOS monolithic IC. The combination of devices provides linear circuit operation with low noise characteristics.

Abstract: A composite transistor suitable for use in monolithic integrated circuits is characterized as having extremely high current gain, stable operation and low leakage current. Two vertical NPN transistors are coupled into a circuit configuration, along with two lateral PNP transistors, that has three terminals. These terminals behave as a single NPN transistor having characteristics that are superior to those of a conventional NPN transistor.

Abstract: An Electrically Erasable Programmable Read-Only Memory (EEPROM) requires only a single voltage applied to a single control gate for both erasing and writing operations. Writing is accomplished by hot channel electron injection to charge the floating gate of a selected device with electrons. Nonselected devices are kept from charging by either floating their sources or grounding their gates. Devices are erased by grounding the source and drain regions and causing the electrons stored in the floating gates to tunnel to the control gate. Preferred ratioing of the intra-device capacitances prevents erasure of nonselected devices during writing.

Abstract: An automatic self-adjusting processing apparatus for plating an object is described. The apparatus has a plating head, an apparatus coupled to the plating head which is responsive to the presence of the object for indicating the relative position of the plating head and the object, and an apparatus coupled to the indicating apparatus for automatically adjusting, if necessary, the relative position of the plating head and the object to a predetermined relative position.