Abstract: A plurality of differential amplifier stages in cascaded in a directly coupled configuration to provide substantial signal gain. The first few stages are cascode coupled to a plural input differential signal combiner which has a single differential output that feeds a full wave differential peak detector. The peak detector therefore has an output that rises as a log function of the signal input. This signal-related voltage is then fed to a differential dc amplifier which in turn drives a meter that indicates the log of the input signal strength. The amplifier cascade is stabilized by a dc feedback loop.

Abstract: A pad for connecting electrical chips in microelectronic circuits includes a passive protective layer overlapping the edge thereof and a bump built up on the connecting pad that had a dimension of the base that is less than that of the pad to prevent the bump from overlapping the edges of the pad and damaging or cracking the underlying structure of the chip during thermocompression bonding of leads to the bump.

Abstract: A discrete, precut strip, lead frame plating system wherein each strip is loaded onto a linked chain, located against plating masks, contacted electrically, plated, dried, and unloaded from the chain in successive sequential fashion.

Abstract: To cut a strip of metal into exact lengths, rollers are brought into contact with the strip and turned by an accurate motor until a pin can be mechanically inserted into a hole in the strip to effect final alignment. If the pin does not successfully enter the hole, a detector halts the system.

Abstract: An interface circuit for converting a digital signal representing a dot-by-dot color video signal into a NTSC signal compatible with a television antenna input precompensates the digital for limitations in typical NTSC receivers. Various methods and circuits for precompensating the luminance amplitude, chrominance and chrominance amplitude content of the digital signal result in perceivably improved contrast and color purity.

Abstract: A high current lateral transistor suitable for intergrated circuit construction is fabricated in the form of a plurality of parallel transistors. Each transistor has an emitter surrounded by a closely confronting collector with the intervening semiconductor acting as the base region. Groups of parallel connected transistors are located on both sides of and distributed along a centerline which contains a number of diffused crossunder resistor elements. Each group of transistors is flanked on both sides by a base contact that is extended perpendicularly away from the centerline and connected by metalization to a resistor element. The resistor elements act to distribute the transistor base currents in a ballasting operation that promotes proper current distribution. Since the resistors are under the oxide the emitter and collector metalization can pass across the centerline region and parallel connect the individual transistors.

Abstract: In an integrated circuit audio power amplifier a 6 db per octave frequency-gain roll off is obtained in a conventional manner by converting a high gain inverter to an integrator and driving the integrator from a current source. A second cascaded stage is also provided so that it operates at lower gain and has a matching high frequency roll off. When such characteristics are combined in cascade the result is a 12 db per octave roll off at the higher frequencies. A flat negative feedback loop is employed to maintain a controlled constant low frequency gain. In the response region located between the 12 db per octave slope region and the constant gain region there is a 6 db per octave slope. The configuration is stable without resorting to frequency sensitive feedback.

Abstract: An error checking apparatus and method for detecting a plurality of errors in a digital data word includes means for generating a unique syndrome word for each one of a plurality of error patterns in a word containing up to N-1 bits in error, where N is the number of bits in said word.

Abstract: This disclosure is directed to an improved semiconductor capacitor structure especially useful in an integrated semiconductor structure with an MOS device and fabrication methods therefor. This semiconductor capacitor is particularly useful for forming the capacitor portion of a single MOS memory cell structure in a dynamic MOS random access memory which utilizes one MOS device in combination with a capacitor. In one specific disclosure embodiment, the semiconductor capacitor comprises a boron (P) implanted region in a substrate of P- type conductivity followed by a shallow arsenic (N) implant into the boron implanted region. The boron implanted region provides a P type conductivity which has a higher concentration of P type impurities than the concentration of impurities contained in the substrate which is of P- type conductivity.

Abstract: In an automatic assembly tape for semiconductor device assembly a continuous tape includes a plurality of sequential metal finger patterns. Each pattern includes a plurality of fingers that extend inwardly to form an array that mates with the bonding pads on a semiconductor device chip. The fingers are bonded to the chip pads so that the chip is then associated with the tape and therefore amenable to further assembly on high speed machines on a reel-to-reel tape handling basis. Each finger pattern includes an inner tear strip ring that initially holds the fingers together in a unitary structure. The fingers are joined to the ring via intermediate weakened regions. After the fingers are bonded to the chip pads, the ring is torn away so as to separate at the weakened regions. Prior to bonding, the fingers are held in precise location and in a common plane. This allows close spaced complex finger patterns and avoids bent fingers which can cause bond failure and possibly clogging of the auto assembly machines.

Abstract: In a monolithic semiconductor integrated circuit, conventional bipolar transistors are fabricated along with thin ion implanted junction field effect transistors, to create BIFET structures. After the conventional isolation diffusion, the surface oxide is stripped off and the semiconductor wafer ion implanted with slow diffusing impurities of a conductivity type, the same as the undiffused surface material. Then the bipolar transistors, along with the junction field effect transistors, are fabricated using conventional oxide masked diffusion processes. The field effect device sources and drains employ the base diffusions of the bipolar transistors while the gate contact is achieved with an emitter diffusion. The field effect device channels are formed at a depth substantially greater than that of the impurities deposited in the original ion implant. If desired, an ion implanted top gate can be established over the channel. The wafer is then annealed and processed in accordance with conventional techniques.

Abstract: A trim structure having a nominal resistance value can be adjusted to have a higher or lower value by a combination of fuse blowing and zener zapping. In the preferred embodiment a pair of integrated circuit pads are employed in a trim structure along with a pair of back-to-back zener diodes, a fuse link, and four resistors. In its initial state, with both diodes and the fuse link intact, a particular or nominal resistance value is available. Blowing the fuse link alone produces a second or highest resistance value. Shorting, or zapping, one zener diode produces a third higher than nominal but lower than highest resistance value. Shorting, or zapping, the other zener diode produces a fourth, lower than nominal, resistance value. Shorting, or zapping, both zener diodes produces a fifth lowest resistance value. Thus, five different resistance values are available using only two integrated circuit pads. If desired, the five resistance steps can be made linear by properly selecting the resistor values.

Abstract: In a system for plating precisely located spots on an intermittently moved strip of metal, a spring loaded pawl on the spot defining mask is positioned to grasp holes in the strip and move just the mask a short distance with the strip so as to insure mask alignment with the strip.

Abstract: A plating head for spot plating a web of moving material that plates faster due to a large planar electrode that faces the plating area and a system of electrolyte channels that inject electrolyte at a high rate from the side of the electrode into the space between the electrode and the plating area.

Abstract: A CMOS integrated circuit power-on reset circuit has two cascaded threshold detectors for independently sensing the supply voltage attaining an amplitude sufficient to operate N and P-channel devices respectively and for providing a reset signal in response to the supply voltage meeting both conditions.

Abstract: An error correcting network adapted for encoding and decoding data transferred to and from a bubble memory has parallel linear encoder/decoder circuits. An error syndrome generated in response to a parity error in an initial read operation is used by one encoder/decoder circuit for correcting the parity error during a subsequent reread of the data. The error syndrome is also stored in a latch for comparison with a second error syndrome generated in response to the data during the reread operation. A true comparison between the two error syndromes verifies that that data has not changed between the two read operations due to a soft error and that the error correction of the first encoder/decoder circuit is valid.

Abstract: An electroplating mask support structure of particular use in the plating of semiconductor chip lead frames in which a support bar has a number of support stations thereon with masking die containing cavities in the stations.

Abstract: A two-phase memory circuit provides for adjusting the precharge voltage of a data line to substantially equal the threshold voltage of a sense amplifier coupled to the data line during a first phase so that a relatively small voltage change on the data line during a second phase can be detected by the sense amplifier.

Abstract: A plating mask of molded unitary configuration with electrolyte admitting openings held to very accurate position and dimension by a molding process in which the mask is formed between two separable molds with forms supported therebetween to exclude material from both mask penetrating and transverse circulation passageways.

Abstract: A process to program ROM's after the insulation, gates, and interconnect circuitry have been formed by using a contact mask to define openings at the depletion cells, which openings extend beside the gates to the sources and drain so as to allow phosphorus dopant to be diffused sideways under the gates to short out the cell.