Abstract: A voltage reference is developed by operating a pair of different threshold CMOS transistors as a differential linear amplifier with the reference voltage value determined as an input offset voltage. The differential amplifier consists of an input stage with controlled offset, a high gain inverter and an output stage which is directly coupled back to the inverting input. The circuit is biased up using a depletion transistor at zero bias and a current mirror configuration for supplying all stages.

Abstract: An interface circuit for converting a digital signal representing a dot-by-dot color video signal into a NTSC signal compatible with a television antenna input precompensates the digital for limitations in typical NTSC receivers. Various methods and circuits for precompensating the luminance amplitude, chrominance and chrominance amplitude content of the digital signal result in perceivably improved contrast and color purity.

Abstract: A current responsive sense amplifier circuit is used in a semiconductor memory. The circuit includes means for reducing the voltage swings that are associated with the binary logic states.

Abstract: A pair of CMOS inverters are cross coupled in a latching configuration. Both inverter supply terminals are coupled to complementary toggles that can render the inverters operative or inoperative. First, the inverters are rendered inoperative. An output switch is coupled between the output nodes so that the inverter's output nodes can be driven to the same potential, thus canceling any offset voltage. An input switch produces sampling over a time interval that extends beyond the output switch on period. After the sampling period, the toggles are operated to turn the inverters on and to produce a latch state determined by the potential change present in the sampling interval.

Abstract: A modulator circuit is disclosed in which a pair of differentially modulated direct currents are mirrored to an output. A control potential acts to vary the modulation without changing the direct current values. A CMOS version of a complete variable gain amplifier is detailed in which the common mode output is V.sub.CC /2 and is not changed with variations in the gain control potential or the input common mode potential.

Abstract: A carrier current receiver employs a comparator driven differentially to square a received data signal. The same drive signal is applied to a sample and hold circuit in which a capacitor is charged to a level that is related to the data signal offset. A voltage-to-current converter responds to the capacitor charge and feeds a current to the input where it acts to correct the offset.

Abstract: In an integrated circuit, back to back zener diodes are connected between circuit pads and each zener diode shunts a resistor in a series string. When a suitable pulse is applied to the pair, the back biased diode will be selectively shorted. Thus, the pulse polarity will determine which diode will short and which resistor will be bypassed. In this manner a pair of pads can be used to selectively short out either one or both of a pair of diodes and a trimming section can be created using only half of the pads required in the case where each zener is contacted separately. The invention is directed to a structure in which the forward biased zener diode is protected so that only the reverse biased diode shorts out when the pulse is applied.

Abstract: An amplifier suitable for carrier current line driver applications is shown. It includes a triangle wave to sine wave shaper circuit and an automatic level control. It incorporates a line surge arrestor circuit that is active even when the transmitting capability is disabled. The circuit is shown in an integrated circuit form, the output of which is capable of being boosted by off-chip components.

Abstract: A pair of transistors, connected as a differential amplifier, is operated so that the transistors run at different current densities. A voltage divider is coupled across a pair of circuit terminals so that a portion of the terminal voltage is coupled to and used to differentially bias the transistors. An amplifier, responsive to the transistors differential output, and coupled to the divider, is used to vary the terminal voltage to force the differential output to zero. The transistor bias voltage thus generated has a positive temperature coefficient of voltage. A forward biased diode, which has a negative temperature coefficient of voltage, is also incorporated into the divider. When the terminal voltage is made equal to the semiconductor bandgap, the two temperature sensitive terms cancel to compensate the reference voltage.

Abstract: A programmable fuse circuit has a fusable polysilicon element programmable in response to an "illegal" condition on existing pins of an integrated circuit. This programmable fuse circuit is incorporated in a programmable partial memory circuit, a reconfigurable format memory circuit, and a chip select circuit.

Abstract: A programming pulse generating circuit, suitable for use on an electrically alterable read-only semiconductor memory, that decouples from the high voltage supply when in a standby condition so as to not draw current from the supply. Alternative voltage supply connections are effected by depletion mode devices.

Abstract: A circuit for clearing selected bytes in a semiconductor electrically alterable memory in which the ground lines for any one column of bytes is isolatable from the ground lines for other columns, all the outputs for the bytes are urged toward a non-clearing condition, and the outputs for only the selected byte are used to introduce a clearing signal that dominates the non-clearing condition.

Abstract: A power transistor design that eliminates thermally initiated secondary breakdown in fast, double-diffused transistors is described. The power dissipation capability is made independent of collector voltage, avoiding safe area restrictions below 0.9 BV.sub.CBO.

Abstract: A circuit to restrain the rise time of a programming pulse generated in an electrically alterable read-only semiconductor memory in which excessively sudden changes in the pulse are capacitively coupled, through active devices that can be built on the chip, to a grounding switch device so as to periodically drain away the control signal used to create the pulse.

Abstract: A wide bandwidth amplifier is shown along with a muting circuit. The output shift between normal operation and mute is kept very small. The amplifier is useful in video disk and audio signal reproduction.

Abstract: A heat molded optical fiber interconnect molds one end of a plastic optical fiber around light emitting surfaces of a light source such as a light emitting diode to provide a highly efficient optical and mechanical coupling between the optical fiber and the light source. In one preferred embodiment an efficient interconnect for coupling large diameter optical fibers has a converging lens heat molded in the other end of the plastic optical fiber to efficiently couple light to another optical fiber or receiver.

Abstract: A trigger circuit with hysteresis is created by driving a latch circuit set and reset terminals through a pair of emitter driven complementary transistors the bases of which are returned to a reference potential V.sub.REF. The hysteresis is set by the V.sub.BE potentials of the complementary transistors. When the input emitters are driven more than one V.sub.BE above V.sub.REF, one transistor will conduct and set the latch. When the input falls below one V.sub.BE below V.sub.REF, the other transistor will conduct and reset the latch. A digital filter is created by coupling a capacitor across the trigger circuit input and digitally driving the capacitor through a transconductance amplifier.

Abstract: A method of annealing an ion implanted semiconductor device using an antireflective dielectric coating on the device for maximizing the coupling of photon radiation into the device. An IGFET device made in accordance with the method, is shown.

Abstract: A linear differential amplifier is fabricated in CMOS and combined with digital control so that an analog input signal can be converted to a selected output polarity. When the amplifier output is coupled directly to the inverting input the noninverting input provides a unity gain voltage follower configuration. To create a unity gain signal inverter, a matched pair of resistors is employed. One resistor is coupled between the amplifier output and the inverting input while the other is coupled between the analog signal input and the inverting input. In operation digital control is employed in switching between the two configurations. The sense of the differential amplifier is reversed when switching between configurations thereby to provide a substantial reduction of the effect of offset potential. To fully compensate the offset potential, a capacitor is periodically coupled across the amplifier input to charge it to the offset potential.

Abstract: A CMOS integrated circuit is made compatible with TTL input signals. A regulator operates the CMOS gates in an array at a voltage that is slightly lower than the supply. The regulator sense circuit is made responsive to an operating gate and to a TTL bias reference. Accordingly, the regulator will compensate for changes in ambient conditions and manufacturing variations so that the gate array devices will reliably respond to TTL level switching signals.