Patents Represented by Attorney Gary C. Honeycutt
  • Patent number: 8314154
    Abstract: A topical anti-aging skin care formulation comprising an effective amount of a benzoquinone, such as CoQ10, plus a synergistic pair of stabilizers and a synergistic pair of whiteners. The stabilizers are octyl salicylate and octyl methoxycinnamate. The whiteners are titanium dioxide and zinc oxide. When proper amounts of these ingredients are used in an aqueous based emulsion formulation, the product will be initially white, and will remain white for an extended period of time.
    Type: Grant
    Filed: September 22, 2008
    Date of Patent: November 20, 2012
    Inventor: Louise Holyfield
  • Patent number: 7757421
    Abstract: A gun protection device comprising an elastic muzzle cover shaped to fit selectively over the muzzle and only a portion of the barrel; and a separate cover for the gun firing chamber, including means for shaping itself to provide a selective fit over the firing chamber.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: July 20, 2010
    Assignee: Mud Brothers Inc
    Inventors: Taylor Tompkins, Todd Liddell
  • Patent number: 7704536
    Abstract: Acid-neutralizing agent contains substantial amount of calcium of an acid-neutralizing ability against various acid chemicals substance for humans, animals, agricultural produces, meat and poultry. And the method of producing the same are provided. An environmental friendly high speed and high press scraping treatment is applied to a calcium-containing substance represented by calcium carbonate-containing substances originating from shellfishes, to eliminate heavy metals and other contamination accumulated on the surface. A heating and baking treatment is applied separately to the different said shellfishes and calcium carbonate-containing minerals and charcoal of bamboo to the temperature and maintaining the temperature not less then the decompose point of each calcium component-containing substance, a sufficient time of heating and baking treatment from 3 hours up to 18 hours depend on materials treated.
    Type: Grant
    Filed: October 1, 2007
    Date of Patent: April 27, 2010
    Inventor: Tieh-Chun Tang
  • Patent number: 7662416
    Abstract: Acid-neutralizing agent contains substantial amount of calcium of an acid-neutralizing ability against various acid chemicals substance for humans, animals, agricultural produces, meat and poultry. And the method of producing the same are provided. An environmental friendly high speed and high press scraping treatment is applied to a calcium-containing substance represented by calcium carbonate-containing substances originating from shellfishes, to eliminate heavy metals and other contamination accumulated on the surface. A heating and baking treatment is applied separately to the different said shellfishes and calcium carbonate-containing minerals and charcoal of bamboo to the temperature and maintaining the temperature not less then the decompose point of each calcium component-containing substance, a sufficient time of heating and baking treatment from 3 hours up to 18 hours depend on materials treated.
    Type: Grant
    Filed: April 27, 2006
    Date of Patent: February 16, 2010
    Inventor: Tieh-Chun Tang
  • Patent number: 7311864
    Abstract: Coffee bean residue is a primary constituent of new thermosetting polymer compositions and articles of manufacture. The articles are made by compression molding and curing of one or more thermosetting polymer resins blended with coffee bean residue. Other additives and fillers may also be included in the compositions.
    Type: Grant
    Filed: February 26, 2005
    Date of Patent: December 25, 2007
    Inventors: David Chi-Ping Chow, Eaman Ochun Tang
  • Patent number: 7003813
    Abstract: A two-way flow control valve for repeatedly dispensing a limited amount of liquid. A float valve is linked to a second valve and storage chamber such that one valve is closed when the other is opened, and vice versa. The chamber fills when the float valve is closed, and empties when the float valve is opened. The assembly is useful for dispensing a liquid cleaner into a toilet tank.
    Type: Grant
    Filed: August 26, 2004
    Date of Patent: February 28, 2006
    Inventor: Clifford G. Krause
  • Patent number: 6632747
    Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer by providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density. This annealing step is selected from a group of four re-oxidizing techniques: Consecutive annealing in a mixture of H2 and N2 (preferably less than 20% H2), and then a mixture of O2 and N2 (preferably less than 20% 02); annealing by a spike-like temperature rise (preferably less than 1 s at 1000 to 1150° C.) in nitrogen-comprising atmosphere (preferably N2/O2 or N2O/H2); annealing by rapid thermal heating in ammonia of reduced pressure (preferably at 600 to 1000° C.
    Type: Grant
    Filed: June 20, 2001
    Date of Patent: October 14, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Hiroaki Niimi, Douglas T. Grider, Rajesh Khamankar, Sunil Hattangady
  • Patent number: 6627955
    Abstract: Structure and fabrication method of a lateral MOS transistor, positioned on the surface of an integrated circuit fabricated in a semiconductor of a first conductivity type, comprising a source and a drain, each having at the surface a region of the opposite conductivity type extending to the centrally located gate, defining the active area of said transistor; and a semiconductor region within said semiconductor of the first conductivity type, having a resistivity higher than the remainder of the semiconductor, this region extending vertically below the transistor while laterally limited to the area of the transistor such that the resistivity under the gate is different from the resistivity under the source and drain regions.
    Type: Grant
    Filed: January 14, 2002
    Date of Patent: September 30, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Craig T. Salling, Zhiqiang Wu, Che-Jen Hu
  • Patent number: 6624068
    Abstract: A lithographic method of forming submicron polysilicon features on a semiconductor substrate, including the steps of coating said substrate with an anti-reflective coating (ARC) comprising two layers having matched indices of refraction (n) and extinction coefficient (k) selected to reduce reflection to less than 1% with 193 nm wavelength exposure. The ARC is subsequently patterned to serve as an etch hardmask. Preferably the ARC mask consists of a first layer of between 300 and 1500 angstroms of silicon rich silicon nitride having an extinction coefficient of from 0.77 to 1.07, and a second layer of between 170 and 320 angstroms of silicon oxynitride having an extinction coefficient of about 0.32.
    Type: Grant
    Filed: August 24, 2001
    Date of Patent: September 23, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Gautam V. Thakar, Reima T. Laaksonen, Cameron Gross, Eric A. Joseph
  • Patent number: 6621064
    Abstract: A light-sensing diode having improved efficiency due to an extended junction geometry that provides more than one level of interaction with the light input.
    Type: Grant
    Filed: May 3, 2001
    Date of Patent: September 16, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiliang J. Chen, Kuok Y. Ling, Hisashi Shichijo, Katsuo Komatsuzaki, Chin-Yu Tsai
  • Patent number: 6469372
    Abstract: A carrier and cover tape assemblage for semiconductor devices which maintains integrity through bake temperature of 125 degrees C is provided by cover and carrier tapes of the same material, such as polycarbonate, and thus having the same thermal properties so that the joining adhesive is placed under minimal stress to cause delamination or distortion.
    Type: Grant
    Filed: May 10, 2001
    Date of Patent: October 22, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Michael L. Hayden, Clessie A. Troxtell, Jr.
  • Patent number: 6456554
    Abstract: An integrated circuit chip comprising an integrated circuit made in a semiconductor substrate, an information write-register circuit having a plurality of gate-controlled components, such as MOS transistors or capacitors, said write-register being integrated into said circuit yet individually addressable; said components having a gate insulator geometry locally susceptible to electrical conductivity upon applying overstress voltage pulses between said gates and said substrate, whereby information can be permanently encoded into said write-register; and a plurality of level shifter circuits to supply said pulses selectively to said component gates according to stored data and controlled by enable commands, said level shifters being integrated into said circuit.
    Type: Grant
    Filed: October 11, 2000
    Date of Patent: September 24, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Tito Gelsomini
  • Patent number: 6452236
    Abstract: A lateral NMOS transistor in a p-well, bordered laterally on each side by an isolation region and vertically by a stopping region, has a n-source and a n-drain, each comprising a shallow region extending to the transistor gate and a deeper region recessed from the gate. The transistor further has in its p-well a region of higher resistivity than the remainder of the well. This region extends laterally from the vicinity of one of the recessed region to the vicinity of the other, and vertically from a depth just below the depletion regions of source and drain to the top of the channel stop region. According to the invention, this region of higher p-type resistivity is created by an ion implant of compensating n-doping, such as arsenic or phosphorus, using the same photomask already used for implants adjusting the threshold voltage and creating the p-well and channel stop.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: September 17, 2002
    Assignee: Texas Instruments, Incorporated
    Inventors: Mahalingam Nadakumar, Song Zhao
  • Patent number: 6435398
    Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads covered by deposited layers of a barrier metal and a bondable metal. After identifying the wafers with off-spec metal layers, the wafers are chemically etched using selective etchants consecutively until the metal layers over the bond pads are removed without damaging the copper metallization. Replacement metal layers are finally deposited over the bond pads. Specifically, the bondable metal, such as gold, is selectively removed by a cyclic dithio-oxamine compound, dissolved in tetra-hydro-furane or acetone. The barrier metals, such as nickel and palladium, are removed by a mixture of inorganic and organic oxidizing acids.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: August 20, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Cheryl Hartfield, Thomas M. Moore
  • Patent number: 6432744
    Abstract: A wafer-scale assembly apparatus for integrated circuits and method for forming the wafer-scale assembly. A semiconductor wafer including a plurality of circuits is provided with a plurality of metal contact pads as electrical entry and exit ports. A first wafer-scale patterned polymer film carrying solder balls for each of the contact pads on the wafer is positioned opposite the wafer, and the wafer and the film are aligned. The film is brought into contact with the wafer. Radiant energy in the near infrared spectrum is applied to the backside of the wafer, heating the wafer uniformly and rapidly without moving the semiconductor wafer. Thermal energy is transferred through the wafer to the surface of the wafer and into the solder balls, which reflow onto the contact pads, while the thermal stretching of the polymer film is mechanically compensated. The uniformity of the height of the liquid solder balls is controlled either by mechanical stoppers or by the precision linear motion of motors.
    Type: Grant
    Filed: October 31, 1998
    Date of Patent: August 13, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Gonzalo Amador, Gregory Barton Hotchkiss, Katherine G. Heinen
  • Patent number: 6432749
    Abstract: Methods for fabricating plastic molded thermally enhanced flip chip packages in which the heat spreaders are assembled in strip format is disclosed, including the first step of providing the heat spreader strip. Inclusion of heat spreaders in strip format allows better automation of the molding process using equipment and fabrication technology known in the industry, and provides a cost effective solution to assembly of high density area array packages. The design of heat spreaders include reduced cross section connecting straps which are readily severed and leave only a small plastic to metal interface for ingress of contamination. Further the designs comprehend either embedded or exposed heat spreaders with methods to hold securely during the molding process.
    Type: Grant
    Filed: August 22, 2000
    Date of Patent: August 13, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Jeremias P. Libres
  • Patent number: 6424027
    Abstract: A semiconductor package substrate for assembling an integrated circuit chip operable at fast ramp rate signals and clock rates, comprising an insulating support having a region for attaching said chip; a pattern of electrical interconnections, disposed on said substrate in one metallization level and operable for transmitting waveforms; and a low pass filter for removing unwanted high frequency components from said transmitted waveforms, comprising a network of inductors and capacitors formed within said one metallization level and positioned substantially within said substrate region for chip attachment.
    Type: Grant
    Filed: September 12, 2000
    Date of Patent: July 23, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Michael A. Lamson, Heping Yue, Truong Ho
  • Patent number: 6413150
    Abstract: A dicing saw blade assembly with parallel blades separated by a spacer and attached to a single spindle on an automated dicing saw, is applicable to precisely separating CSP or MCM devices which have been fabricated on a polymeric substrate. Two parallel cuts are made simultaneously in the scribe streets of the substrate to separate the flip chip devices. The substrates are diced from the bottom side, thereby allowing use of thin blades for separating devices having relatively thick chips, as well as chips with attached heat spreaders.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: July 2, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: David B. Blair
  • Patent number: 6396136
    Abstract: A package for a flip chip integrated circuit including an interposer with electrical interconnecting for signal, power, and ground contacts. Routing is accomplished on only two conductor layers through the use of selective planes and buses. Multiple power planes are provided on a single conductor level to support circuits having different operating voltages. A unique cavity down BGA package for a flip chip interconnected integrated circuit is provided by adhering the interposer to a thermally conductive stiffener or base, and using solder balls to attach the frame to the base and interposer. The assemblage forms a chip cavity with interconnecting vias to external BGA solder balls terminals located in the perimeter frame.
    Type: Grant
    Filed: December 22, 1999
    Date of Patent: May 28, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Navinchandra Kalidas, Masood Murtuza, Raymond W. Thompson
  • Patent number: 6392263
    Abstract: A densely integrated pixel, fabricated by CMOS technology, comprises a photodiode formed by a n-well, with cathode, surrounded by a p-well; a reset MOS transistor formed such that its polysilicon gate is positioned, for diode control, across the junction formed by p-well and n-well regions, and its source is merged with the photodiode cathode; and a sensing MOS transistor formed such that its source is combined with the drain of the reset transistor and its gate is electrically connected to the source of the reset transistor. In the pixel of the invention, the photodiode leakage current is greatly reduced, because no n+/p-well junction is connected to the photodiode, and the fill factor is improved, because the pixel size is much reduced.
    Type: Grant
    Filed: May 15, 2001
    Date of Patent: May 21, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Zhiliang J. Chen, Kuok Y. Ling, Hisashi Shichijo, Katsuo Komatsuzaki, Chin-Yu Tsai