Abstract: A structure and method for forming a hermetically sealed semiconductor chip having an active and a passive surface and four edge sides, each edge side having only a single plane; said active surface having an integrated circuit including multiple deposited layers and a plurality of contact pads, said contact pads having bondable and non-corrodible surface; said deposited layers having exposed portions at said side edges; a protective overcoat impermeable to moisture overlying said integrated circuit; and a continuous sealant layer impermeable to moisture overlying all area of said four side edges, whereby said edge sides are sealed and said chip is rendered hermetic.

Abstract: A method for loading solder particles (14) onto an substrate comprising applying a flux (18) directly onto solder particles (14) either prior to or following adhering the solder particles (14) onto adhesive areas (30) of an adhesive coated film (20). The adhesive areas (30) of the adhesive coated film (20) are oriented to correspond with contact pads (42) of a substrate (16). The adhesive coated film (20) is aligned with the substrate (16) to transfer the solder particles (14) to the contact pads (42). The solder particles (14) may then be reflowed to securely attach the solder particles (14) to the contact pads(42).

Abstract: A battery cell bypass protection technology for use with NiH2 (or other energy storage) cells on a spacecraft or other high reliability application. The device is a thermally activated switch, designed to bypass the current around a failed (open) or failing cell so that the other cells in the battery are unaffected. One unique aspect of the design is a “pre-loaded” compression action, solder shorting mechanism. Another unique aspect is that the construction employs series redundant heaters and blocking diodes in multi-chip packages. These unique aspects provide consistent and complete shorting to provide a low-resistance cell bypass in any orientation on earth (1g) or in orbit (0g). Another unique aspect is the use of non-lead-based solder that minimizes “creep” over time and temperature.

Abstract: A high density memory module is disclosed comprising a first packaged integrated circuit memory device having therein a first electrically insulating carrier and a first conductive routing pattern integral with said first carrier, and at least a first semiconductor circuit chip; a second packaged integrated circuit memory device electrically connected to said first device, wherein said first and second devices form a module; said second packaged integrated circuit device having therein a second electrically insulating carrier and second conductive routing pattern integral with said second carrier, and at least a second semiconductor circuit chip; and said second conductive routing pattern including means for modifying the architectural organization of said module.

Abstract: A substrate for solder ball assembling a semiconductor device substantially parallel onto said substrate, said device having a plurality of terminals arrayed on a warped surface, comprising an electrically insulating surface including a plurality of discrete metallic areas; said areas having locations matching the locations of said device terminals, and further being suitable for solder ball attachment in surface mount reflow operation; and said areas further having at least one characteristic suitable for accommodating said device warping in solder reflow operation, whereby areas having higher amounts of said characteristic cause said solder balls to become thinner during reflow, resulting in lower solder joint heights, relative to the heights of the remaining solder joints.

Abstract: A semiconductor assembly comprising a semiconductor chip having an active and a passive surface, said active surface including an integrated circuit and a plurality of bonding pads; said bonding pads having a metallization suitable for wire bonding; an array of interconnects of uniform height, each of said interconnects comprising a wire loop substantially perpendicular to said active surface, each of said loops having both wire ends attached to a bonding pad, respectively, and a major and a minor diameter, said loops being oriented parallel with regard to the plane of the opening and having constant offsets in both direction and magnitude of their apex relative to their bonding pad centers; said wire loops having sufficient elasticity to act as stress-absorbing springs; an electrically insulating substrate having first and second surfaces, a plurality of electrically conductive routing strips integral with said substrate, and a plurality of contact pads disposed on said first surface, with attachment materia

Abstract: A system (10) for coupling conductive pellets (40) to a component (12) of an integrated circuit has a substantially planar ribbon (14) that includes a conductive material. A punching apparatus (16) and (38) penetrates the ribbon (14) to form the conductive pellets (40). The punching apparatus (16) and (38) also moves relative to the component (12) to the conductive pellets (40) to the component (12).

Abstract: An apparatus for mass fabrication of a semiconductor assembly comprising optical sources for supplying radiant energy for rapid and controlled heating of a multitude of integrated circuit chips and substrates. The resultant thermal profile is applied to reflowing solder interconnections as well as to filling chip-to-substrate gaps with polymeric precursors whereby any mechanical stress detrimental to mechanically weak solder joints and dielectric layers is avoided. The apparatus contains dispensing equipment with multiple degrees of freedom so that the chips and substraters to be assembled do not have to be moved within or from the apparatus. Processing in controlled environment is feasible.

Abstract: A method for attaching particles (12) to a substrate (14), comprising the steps of aligning particles (12) attached to an adhesive sheet (35) with contact pads (42) of a substrate (14), transferring thermal energy (38) to the adhesive sheet (35) by maintaining a temperature below the melting point of particles (12), and removing the adhesive sheet (35) prior to reflow, is disclosed. The adhesive sheet (35) may be composed of an adhesive coating (22) laminated to a film (24). The particles may be composed of a variety of compositions, including compounds such as solder or plastic, for example.

Abstract: An architecture and method of fabrication for an integrated circuit having a reinforced bond pad comprising at least one portion of the integrated circuit disposed under the bond pad; and this at least one circuit portion comprises at least one dielectric layer and a patterned electrically conductive reinforcing structure disposed in this at least one dielectric layer.

Abstract: A semiconductor assembly and method of fabrication comprising an integrated circuit chip, an electrically insulating substrate, a multitude of solder balls for interconnecting both parts while spacing them apart by a gap, and a polymeric encapsulant filling the gap. The method of fabrication includes heating and cooling cycles, based on stress modeling, such that all mechanical stress levels in the dielectric layers of the circuit chip and in the solder balls are reduced to levels safe for operating the semiconductor assembly.

Abstract: A packaged semiconductor device and a method for burn-in and testing are disclosed. The package comprises a carrier having a pattern of contact pads for electrical connection, and also a pattern of testing pads for electrical characterization such that their location, size and composition allows a conversion to contact pads after the device has been electrically characterized following burn-in. Furthermore, an adapter and a method for burn-in and testing are disclosed for use in testing a variety of different semiconductor devices. The adapter comprises a carrier having a pattern of testing pads bordering the carrier outline, and routing strips which are structured such that the carrier is adaptable to the package of the device being tested.

Abstract: An improved mold system (20) is provided. The mold system (20) includes a mold (30) having a mold cavity (28). A pot (22) is connected to the mold cavity (28) through a boomerang runner system (24). The boomerang runner system may include a boomerang passage (25) having an inner curvilinear surface (44) and an outer curvilinear surface (42).

Abstract: An apparatus for the fabrication of a semiconductor assembly and a method of underfilling flip-chip devices are disclosed. The apparatus for multiple controlled dispensing of polymeric precursors filled with silica and anhydrides comprises a center feed tube supplying the proecursor; a header connecting the center tube to a plurality of distribution tubes, whereby the distribution tubes acquire predetermined distances from the center tube; a nozzle at the end of each distribution tube; and these nozzles having increasingly larger cross sections, the farther the respective distribution tube is positioned from the center tube, whereby the dispense rate of the precursor remains the same for all distribution tubes.

Abstract: The invention provides a low inductance semiconductor package for RF circuits having a flat leadframe with internal leads formed upward to be in very close proximity to the die mount pad. The die mount pad is exposed through the package backside and serves both as a ground plane and as a heat spreader. The external leads are flat and extend beyond the package edge so that good solder connections to a printed wiring board can be made and inspected. The lead tips exposed beyond the package further provide a position for mold clamping and for test probing the device.

Abstract: A hybrid radio frequency (RF) power device is provided which comprises: a flange (10) and an arrangement of die blocks (30) disposed about the flange (10), where the arrangement of die blocks (30) has die blocks (30a-30d) organized in a plurality of rows and a plurality columns, where the device may further comprise a substrate (15) disposed between the flange (10) and the arrangement of die blocks (30), and a first die block (30a) connected to a second die block (30b) by a conductor (42c) having a length of half a wavelength.

Abstract: A lightweight packing reel for storing encapsulated semiconductor devices which may be baked for extended periods of time at temperatures sufficiently high to desorb moisture from the packages, and which allows efficient flow of heat and air through the tape and reel assemblage is provided.

Abstract: A method for assembling electronic devices by moving particles (12) on an adhesive sheet (35) having a plurality of adhesive areas (30), comprising the steps of loading the particles (12) onto the adhesive sheet (35) and transferring kinetic energy from a mechanical device (39) to the particles (12) for moving the particles (12) is disclosed. The adhesive sheet (35) may be composed of an adhesive coating (22) laminated to a film (24). The particles (12) may be composed of a variety of materials, including minerals and compounds such as solder or polymers.

Abstract: A leadframe having the desirable features of palladium plated leadframes, such as compatibility with both wire bonding and solder reflow, as well as good adhesion to molding compounds is provided by plating the interior lead frame portions with one microinch of palladium and the external leads which contact solder with three microinches of palladium. A low cost method for fabricating the leadframe based on a unique combination of proven processes is provided.

Abstract: A method and system for electroplating a metal coating onto a continuous part, such as the leadframe stock used in packaging integrated circuits, whereby the method comprises plating metal from a series of plating baths having the same or compatible chemical composition, supplying a continuous electrical connection between the D.C. power supply via a rotating contact held in intimate contact with the cathode, and cooling the contact by using the plating solution itself.