Patents Represented by Attorney Gary C. Honeycutt
  • Patent number: 5538230
    Abstract: A single piece, high purity, full density semiconductor wafer holding fixture for holding a multiplicity of wafers and consisting essentially of chemical vapor deposited silicon carbide (CVD SiC). The wafer carrier is advantageous for the fabrication of electronic integrated circuits where high temperatures and/or corrosive chemicals present, where dimensional stability of the holder is advantageous to the process or where introduction of contaminating elements is deleterious to the process. The method for making such an article comprises shaping a substrate, e.g. graphite, which on one surface has the form of the desired shape, said form comprising raised longitudinal sections to support the silicon wafers at the edges of the wafers, chemically vapor depositing a layer of silicon carbide onto the substrate, removing the substrate intact or by burning, machining, grinding, gritblasting and/or dissolving, and grinding the silicon carbide in any areas where a more precise dimension is required.
    Type: Grant
    Filed: August 8, 1994
    Date of Patent: July 23, 1996
    Inventor: Thomas Sibley
  • Patent number: 5526421
    Abstract: A voice transmission system including a microphone (13) in combination with active sound cancellation means comprising a speaker (14) and a signal processor (17) for generating a mirror-image waveform with respect to the signal generated when speaking into the microphone. The mirror-image waveform is used to activate the speaker (14) thereby cancelling the user's voice. This provides the user with complete privacy, since the cancellation prevents the user's voice from being overheard by others, even in a crowded area.
    Type: Grant
    Filed: February 16, 1993
    Date of Patent: June 11, 1996
    Inventors: Douglas L. Berger, Donald G. Jones
  • Patent number: 5514439
    Abstract: A fixture for supporting a semiconductor wafer during rapid thermal processing, comprising a two-piece assembly of parts, one of which is a silicon carbide wafer support section having a wafer contact face shaped by direct contact with a mold, during its formation by chemical vapor deposition. The other piece is a holding section shaped to keep the wafer support section in place within the reactor. The two-piece assembly improves thermal performance, compared with a one-piece fixture, because the rate of heat conduction across the gap between parts is always less than the rate of heat conduction through a one-piece fixture having the same dimensions.
    Type: Grant
    Filed: October 14, 1994
    Date of Patent: May 7, 1996
    Inventor: Thomas Sibley
  • Patent number: 5443649
    Abstract: A single piece, high purity, full density semiconductor wafer holding fixture for holding a multiplicity of wafers and consisting essentially of chemical vapor deposited silicon carbide (CVD SiC). The wafer carrier is advantageous for the fabrication of electronic integrated circuits in a vertical furnace, where high temperatures and/or corrosive chemicals are present, where dimensional stability of the holder is advantageous to the process, and where introduction of contaminating elements is deleterious to the process. The method for making such an article comprises shaping a substrate, e.g.
    Type: Grant
    Filed: November 22, 1994
    Date of Patent: August 22, 1995
    Inventor: Thomas Sibley
  • Patent number: 5444018
    Abstract: A contact for a semiconductor device has a via extending through a dielectric and collimated titanium in the via. Depositing titanium by collimation places sufficient metal into high aspect ratio contacts to make good electrical connection. The collimated titanium may be reacted in a nitrogen containing ambient to form a titanium silicide layer at the bottom of the contact and a titanium nitride layer over the titanium silicide layer. The titanium silicide layer provides good electrical contact to a device in a silicon semiconductor substrate and lowers contact resistance. Tungsten may be deposited over the colliminated titanium to form a conductor layer. The titanium nitride layer provides a sticking layer for the tungsten. The contact structure and the method are useful in high aspect ratio contacts present in VLSI multilevel interconnected devices such as dynamic random access memories.
    Type: Grant
    Filed: October 13, 1993
    Date of Patent: August 22, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Dennis J. Yost, Thomas D. Bonifield, Roc Blumenthal
  • Patent number: 5440769
    Abstract: A specialty item for supporting a baby's head, while the baby is held by a mother's arm, including a soft foam pad shaped to support a baby's head, combined with a fabric case, shaped for attachment around a mother's arm, to thereby fix the pad in place. The baby's head rest provides greater comfort for both mother and baby, whenever the baby is held for feeding or cuddling. In warm weather the item also avoids the tendency for perspiration to collect on the mother's arm and on the baby's neck and head.
    Type: Grant
    Filed: August 26, 1994
    Date of Patent: August 15, 1995
    Inventor: Kassandra Thomas
  • Patent number: 5388144
    Abstract: A simple, inexpensive device for automatically dialing an emergency number in response to a signal generated by a smoke alarm or other security system. The device includes a cam and cam follower, arranged in combination with an electrical switch connected to a telephone line, so that the motion of the cam follower causes the switch to create a dialing function without human intervention, and without electrical power, other than the dial-tone voltage from the telephone line.
    Type: Grant
    Filed: September 13, 1993
    Date of Patent: February 7, 1995
    Inventor: John D. Nichols
  • Patent number: 5352913
    Abstract: A method of reducing gated diode leakage in trench capacitor type field plate isolated dynamic random access memory devices is disclosed. Trenches are etched into a face of a body of semiconductor material. Storage nodes surrounding the trenches are created. A polysilicon layer is formed on the trench walls. A storage dielectric layer is formed on the trench walls, adjacent to the layer of polysilicon on the trench walls, so that the layer of polysilicon on the trench walls lies between the storage dielectric layer and the storage node. The layer of polysilicon on the trench walls reduces leakage current from the storage node. A trench type field plate isolated random access memory cell structure is also disclosed.
    Type: Grant
    Filed: March 2, 1994
    Date of Patent: October 4, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Gishi Chung, William R. McKee, Clarence W. Teng
  • Patent number: 5339218
    Abstract: A circuit board assembly comprising a surface-mounted microelectronic device combination, including a metallic base member having an insulating layer thereon, and a plurality of electrically conductive mounting pads patterned on the insulating layer. At least one pair of hermetically sealed diodes is bonded to the pads, such that each diode of each pair has one terminal bonded to a first pad, and the other terminal bonded to second and third pads, respectively. For example, a two-diode combination is provided with three leads, one for each pad, whereby various lead connections may be selected, for the purpose of using each diode separately; or for the purpose of using both diodes, either in series or in parallel.
    Type: Grant
    Filed: May 20, 1993
    Date of Patent: August 16, 1994
    Assignee: Microsemi Corporation
    Inventor: Robert Veeck
  • Patent number: 5327327
    Abstract: The multi-chip circuit module of the invention comprises a plurality of circuit chips assembled in a laminated stack. Each chip includes a plurality of layers of thin film interconnect patterns in the normal configuration, except for the final layer or layers, which comprise a reroute pattern that locates all circuit input and output pads along a single edge of each chip. The relocated pads are provided with contact bumps to facilitate the addition of a bonded lead to each I/O pad extending therefrom to a point beyond the edge of each chip. Thus, upon lamination the protruding tips form an array of leads on a single lateral face of the laminated chip stack.
    Type: Grant
    Filed: October 30, 1992
    Date of Patent: July 5, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Dean L. Frew, Mark A. Kressley, Arthur M. Wilson, Juanita G. Miller, Philip E. Hecker, Jr., James Drumm, Randall E. Johnson, Rick Elder
  • Patent number: 5321277
    Abstract: A base for a multi-chip module that provides for built-in testability. Active test components are embedded in a module substrate. These test components primarily consist of boundary scan cells that comply with the IEEE 1149.1 test standard. The scan cells are connected to each other, and are connected to interconnection paths among chips and to individual chips, thereby partitioning the module into testable partitions. These partitions permit testing of chip interconnections, chip functionality, and module functionality. Scan cell connections may be mask programmable so that the same multi-chip module base can be used for many different multi-chip module configurations.
    Type: Grant
    Filed: August 26, 1993
    Date of Patent: June 14, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Steve E. Sparks, Darvin R. Edwards, Katherine G. Heinen
  • Patent number: 5296385
    Abstract: Several process flows are proposed for achieving suitable wafer backside structures for integrated RTP-based device processing. The wafer backside conditions proposed here can be adapted for integrated fabrication process flows based on multiple integrated single-wafer and rapid thermal processing (RTP) cycles. These backside conditions ensure repeatable RTP uniformity and accurate pyrometry calibrations and measurements. The use of a highly doped layer near the wafer backside ensures negligible infrared transmission and repeatable RTP-based process uniformity, both for the high-temperature and the lower temperature RTP-based processes such as low-pressure chemical-vapor deposition of silicon. Two backside layers are used (oxide and nitride) to prevent dopant outdiffusion and backside oxide growth due to thermal oxidation. Moreover, the backside silicon nitride layer preserves uniform backside emissivity throughout the entire flow.
    Type: Grant
    Filed: March 3, 1992
    Date of Patent: March 22, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Mehrdad M. Moslehi, John Kuehne, Lino Velo
  • Patent number: 5262958
    Abstract: A processor (10) is disclosed which uses a B-spline interpolator (14) to produce a plurality of zero-level spline coefficients c.sup.0 (n). This set of coefficients may be fed to a B-spline generator (16) to produce an approximation of the input signal, and/or may be multiplied by a set of coefficients Bn to produce a set of first-level wavelet coefficients d.sup.-1 (n). The zero-level spline coefficients are also used to create first-level spline coefficients c.sup.-1 (n). The first-level spline and wavelet coefficient c.sup.-1 (n) and d.sup.-1 (n) may be submitted to a respective B-spline generator (22) or B-wavelet generator (24) to produce a first-level spline signal components and a first-level wavelet signal component for extraction of data from the original signal. The signal may in a similar fashion be decomposed to any level of resolution desired. The signal components may then be processed, and an improved signal then reassembled from the last-level spline and the processed wavelet signals.
    Type: Grant
    Filed: April 5, 1991
    Date of Patent: November 16, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Charles K. Chui, Andrew K. Chan
  • Patent number: 5256566
    Abstract: A method for in-situ doping of deposited silicon is disclosed. The method utilizes low temperature of approximately 560.degree. C., low pressure of approximately 300 mTorr, and low phosphine to silane ratio of approximately 0.0008 to form phosphorus doped silicon. The method is manufacturable in an automated LPCVD reactor. It allows relatively uniform defect free silicon films of low resistivity and good conformality and step coverage to be deposited at sufficient deposition rates over large semiconductor wafer lots for high wafer throughput.
    Type: Grant
    Filed: May 8, 1991
    Date of Patent: October 26, 1993
    Assignee: Texas Instruments Incorporated
    Inventor: Dane E. Bailey
  • Patent number: 5229306
    Abstract: A method for gettering metal atoms (28) from a subsequently contaminated silicon substrate (12) is disclosed. A smoothed or polished first surface (16) has a thin germanium silicon layer (20) deposited thereon. A silicon layer (24) is deposited onto the germanium silicon layer (20) to seal the layer (20) between the substrate (12) and the silicon layer (24). Electronic components (26) are fabricated on a second surface (14) of the silicon substrate (12) which causes the metal atoms (28) to contaminate the substrate as a result of contamination in normal processing (12). As the substrate (12) is heated during normal processing of the devices, metal atoms (28) in the substrate of a result of contamination, diffuse in the substrate (12) to the misfit dislocations at the germanium-silicon (20)/silicon interface.
    Type: Grant
    Filed: December 27, 1989
    Date of Patent: July 20, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Keith J. Lindberg, Greg Gopffarth, Jerry D. Smith
  • Patent number: 5225037
    Abstract: A flexible polyimide film is used to support an array of precisely located contact bumps which are used to probe die on a wafer of semiconductor circuits, or an unmounted integrated circuit die, several integrated circuits, or hybrid devices. By utilizing a standard I/O contact pattern for the flexible film and fabricating the membrane assembly of interconnects on an aluminum substrate, it is possible to produce a more reliable probe card, while reducing the fabrication time and costs for the probe card. The polyimide film must be selected to have a CTE of 3 to 5, which is only about 1/5 to 1/7 as great as the CTE of the aluminum substrate on which the film is formed. This produces a critical degree of compressive stress in the polyimide film, and a resulting "bow" of the film when the central area of the aluminum is etched away.
    Type: Grant
    Filed: June 4, 1991
    Date of Patent: July 6, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Richard A. Elder, Arthur M. Wilson, Susan V. Bagen, Juanita G. Miller
  • Patent number: 5219264
    Abstract: A mobile robot or automatic guided vehicle having a multijointed robot arm. The robot arm has a gripper and charge coupled device camera mounted at the free end of the arm. The gripper is for engaging, holding and releasing workpieces. The robot arm transfers workpieces to and from process machines or storage areas. The robot arm finds the workpiece or the place to set it down by looking at two light emitting diodes placed a known distance and orientation away from the workpiece or set down place. The robot arm and camera are controlled by a computer on board the vehicle. The automatic guided vehicle and robot arm are used to transfer workpieces from place to place in an automated manufacturing environment.
    Type: Grant
    Filed: April 10, 1990
    Date of Patent: June 15, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Virge W. McClure, Nai-Yung Chen
  • Patent number: 5208169
    Abstract: A high voltage bipolar transistor (10) is fabricated in an N- HV/epitaxial well (12) formed by an N- substrate implant and the overlying portion of the N- epitaxial layer 12b. The N- substrate implant replaces the normal buried N+ collector layer, in effect extending the depth of the epitaxial layer to increase junction breakdown voltages. The collector is formed by buried N+ collector regions (14a and 14b) formed adjacent to, and on either side of, the N- substrate implant. The transistor is fabricated conventionally in the N- HV/epitaxial well, except that, to further enhance high voltage performance, P+ extrinsic base regions (23a and 23b) can be extended using optional deep P+ implants (reducing curvature effects which correspondingly reduces electric field, and thereby inhibits premature junction breakdown).
    Type: Grant
    Filed: June 28, 1991
    Date of Patent: May 4, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Rajiv R. Shah, Stephen A. Keller
  • Patent number: 5208001
    Abstract: A method of removing impurities from low grade silicon is provided comprising adding a zirconium compound to the low grade silicon for adsorbing the impurities.
    Type: Grant
    Filed: June 20, 1991
    Date of Patent: May 4, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: James K. Truitt, Mohendra S. Bawa
  • Patent number: RE34311
    Abstract: A transport mechanism (40) for transporting a semiconductor slice cassette between a clean carrier (10) and a process machine comprises a housing (41) having a forward portion (42) positioned in the people-occupied area of the clean room and a rear portion (46) positioned in the process machine area aerodynamically isolated from people. A moveable glider plate (50) is adapted to receive the carrier (10) and is initially positioned in an aperture provided in the upper surface of forward portion (42). A gearing mechanism (54) is provided which cooperates with glider plate (50) to move the semiconductor slice cassettes mounted on the base of carrier (10) between forward portion (42) and rear portion (46).
    Type: Grant
    Filed: January 13, 1989
    Date of Patent: July 13, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Edwin G. Millis, Alton D. Lewis, Thomas C. Bimer