Abstract: In the manufacture of semiconductor devices it is often times necessary to use photomasks. It has been found that silicon material is useful as see-through photomasks when deposited on a thin film of glass. After deposition the silicon is etched to form the mask. A suitable etchant, which may be used and which does not undercut patterned material formed over the silicon, may be derived from a composition of CCl.sub.4 + N.sub.2 + Cl.sub.2 and in some instances + HCl. This etchant may also be used in patterning polysilicon leads on various silicon devices such as charged coupled devices without undercutting of the leads.

Abstract: A planar optical waveguide is optically coupled to a source of laser radiation for propagation of light therein. The optical waveguide comprises a substrate having a first light transmitting layer deposited thereon and a second light transmitting layer deposited on the first layer. Both light transmitting layers are made of materials having indexes of refraction compatable with a semiconductor material taken from the group consisting of III-V semiconductor compounds and mixed ternary III-V semiconductor compositions. The index of refraction of the second light transmitting layer is higher than the index of refraction of the first light transmitting layer thereby providing optical confinement in the second layer.

Abstract: This disclosure concerns optical waveguides of semiconductor material through which light is adapted to be propagated. The optical waveguides comprise respective first and second layers of semiconductor material of the same conductivity type, wherein one of the semiconductor layers has a relatively low refractive index, while the other semiconductor layer has a relatively high refractive index, with the light being adapted to be propagated through the semiconductor layer having the relatively high refractive index. The optical waveguide structures are characterized by having the semiconductor layer through which the light is to be propagated so formed as to include each of its two side surfaces and top surface as being planar faceted growth surfaces of extreme smoothness to avoid scattering light as it is being propagated therethrough, thereby minimizing losses.

Abstract: Disclosed is a method for providing electronic semiconductor devices and the devices produced thereby utilizing an orientation dependent etch to selectively provide grooves in a monocrystalline silicon substrate having a crystal orientation of (110). By selectively etching with an orientation dependent etch to provide deep grooves having substantially parallel sidewalls and thereafter refilling with an appropriate material of the appropriate conductivity, a plurality of semiconductor electronic devices are provided.

Abstract: Disclosed are improved field-effect and bipolar semiconductor devices and the method of making them, wherein maximum junction control provides highly predictable device parameters. Low temperature epitaxial depositions provide tight junction thickness and resistivity control, and an orientation dependent etch forms grooves circumscribing portions of the host substrate and overlying epitaxial layers to provide dielectrically isolated single crystalline mesas utilized in forming electronic devices.

Abstract: Disclosed is a method of forming patterned electron beam resists from styrene-diene block copolymers and the resists formed thereby. A thin film of a styrene-diene block copolymer is applied to a support and is subjected to an electron beam scan. An electron beam irradiates a portion of the copolymer film according to a programmed pattern; the copolymer cross links where irradiated, thus causing the irradiated portion of the copolymer to become insoluble in a solvent. The balance of the copolymer remains soluble in the solvent, dissolves and is removed, resulting in the desired pattern of openings.

Abstract: A miniaturized multi-element infra-red sensor comprises a Dewar tube having a tubular core and a jacket with an infra-red transmitting window at the upper end of the jacket. A multi-element infra-red sensing array is mounted on a printed circuit member at the upper end of the core. Wires are interconnected between the infra-red sensing elements of the array and leads printed on the printed circuit member which radiate out to the margin of the latter. Conductors extending longitudinally of the core have their upper ends bent around the edge of the printed circuit member and attached to the outer ends of the printed leads. In the manufacture of the device, the conductors are initially formed as part of a lead frame, which is assembled with the printed circuit member, prior to mounting of the array on the printed circuit member.

Abstract: Disclosed is an improved optical thin film coating system comprising all essential elements of resistive and electron beam evaporation systems, chemical vapor deposition systems and reactive plasma deposition systems. Sequences of cleaning and deposition processes which previously required moving substrates through several chambers are performed in a single vacuum chamber. The evaporative sources also efficiently vaporize solid materials to provide reactive gases for reactive plasma and chemical vapor deposition processes, which were previously difficult or impossible to perform. Substrate movement, masking, and monitoring means previously used with evaporative sources are used to control thickness and uniformity of films deposited by chemical vapor and reactive plasma processes, to provide optical quality films.

Abstract: A process for fabricating a monolithic integrated circuit having matched semiconductor devices and P-N junction isolation regions, with the collector regions for the semiconductor devices of one polarity type and the isolation regions being formed by up-diffusing impurities from a selected surface of a substrate of one conductivity type though an epitaxial layer of opposite conductivity type formed thereon, so that such collector regions are surrounded by material of opposite conductivity type, and the P-N junction isolation regions selectively isolate semiconductor devices of opposite polarity type from other circuit elements, wherein such collector regions and P-N junction isolation regions have retrograded impurity concentration profiles.

Abstract: A logic gate using a single transistor having two emitters interconnected by a resistor which is center-tapped to the transistor base. The collector is connected through a load resistor to the DC supply rail.A logic gate using a pair of IGFETS having sources connected together, the drains connected through a common resistor to a DC supply rail. The gates are connected through diodes to the common sources of the channels.Various logic gate functions, including EXCLUSIVE-OR and EXCLUSIVE-NOR functions based on these gates.

Abstract: This disclosure relates to methods of producing thin layers of silicon as well as thin layers of silicon on insulating substrates such as silicon dioxide or polycrystalline silicon by forming either an n- layer of single crystal silicon over a p++ layer of single crystal silicon or a p- layer of single crystal silicon over an n++ layer of single crystal silicon and then removing either the n++ or p++ single crystal substrate, as the case may be, by utilizing an etch which will only etch the n++ or p++ region and will stop when the n- or p- region, as the case may be, has been reached.

Abstract: Disclosed is a vapor deposition reactor comprising a series of individual gas cells respectively isolated from each other and containing a particular reactive or non-reactive gas required for one stage in a deposition process. Each cell is provided with an independent temperature control. A substrate is mounted on a carrier and transported through the series of individual cells so that vapor depositions or other related processes may be conducted or performed upon the substrate. Chemical vapor deposition processes such as growth of epitaxial layer, deposition of polycrystalline silicon, nitride, oxide or metals on a substrate may be performed within the reactor. The cells are isolated by viscous loss seals formed by the propinquity of restricted openings in the reactor to substrate carrier configuration.

Abstract: An insulated gate field effect transistor having a self-aligned gate, reduced capacitance, and lower surface step heights is fabricated with the use of a silicon nitride layer which serves first as a diffusion mask, than as an oxidation barrier, and ultimately as a gate dielectric. In an alternate embodiment, lower threshold voltages are achieved by replacing the initial gate dielectric with a thinner dielectric having a reduced surface state density.

Abstract: A method of making a semiconductor device is disclosed in which a plurality of generally parallel conductors are provided, at least one of which has a mounting portion thereon. A semiconductor wafer is coupled to the mounting portion while means are provided for coupling the other conductors to the semiconductor wafer. An integrally molded mass of insulation material embeds the semiconductor wafer, and the mounting portion, as well as the means connecting the conductors to the semiconductor wafer.

Abstract: A coaxial-lead, double-plug, glass-sealed semiconductor diode is provided with gold-germanium alloy contacts metallurgically bonded to Dumet alloy plugs.

Abstract: A display device in which a thin layer of a lyotropic nematic mesomorphic composition is utilized to diffuse light from a source toward an observer by applying a suitable voltage, for example, 20 volts for a 1 mil layer. One form of the device transmits light through the layer. A second form of the device uses light diffused and reflected to the observer.

Abstract: A display device in which a thin layer of a lyotropic nematic mesomorphic composition is utilized to diffuse light from a source toward an observer by applying a suitable voltage, for example, 20 volts for a one mil layer. One form of the device transmits light through the layer. A second form of the device uses light diffused and reflected to the observer.

Abstract: Disclosed is a radiation emitting diode in which a first layer of N-type GaAs and a second layer of N-type GaAlAs are formed on an N-type GaAs substrate. A localized zinc diffused region extends through the second layer and partially into the first layer to form a buried junction. Because of the higher bandgap energy of GaAlAs than of GaAs, the current density in the GaAlAs portion of the p-n junction is greatly reduced compared to that in the GaAs portion and the non-radiative surface components of current are greatly reduced. This results in a buried junction structure in which the radiation emitting region is removed from the surface. The buried junction structure provides devices having improved linearity of the radiant output power versus current characteristics and reduced degradation of radiant output power at constant current with time.

Abstract: A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, using process specifications and design rules of the same general character previously developed for single-level metal gate CMOS devices. An electron injector junction (p+/n) is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.

Abstract: A dual injector, floating-gate MOS non-volatile semiconductor memory device (DIFMOS) has been fabricated, wherein the electron injection means comprises a p+n+ junction, the n+ region thereof having a critical dopant concentration, controlled by ion implantation. The junction is avalanched to "write" a charge on the floating gate, and a hole injector junction (n+/p-) is avalanched to "erase" the charge. An MOS sensing transistor, whose gate is an extension of the floating gate, "reads" the presence or absence of charge on the floating gate. In a preferred embodiment, the hole injection means includes an MOS "bootstrap" capacitor for coupling a voltage bias to the floating gate.