Abstract: Memory failure detection apparatus is disclosed which is used with a large capacity memory that is organized in banks of memory, and with which error correction circuitry is used to correct correctable errors and provide an indication of same. The detection apparatus is responsive to the error indications and to a bank select addressing signal to provide and store error counts for a bank or banks of memory located on each memory board. A system processor periodically reads the error counts and responds to same to provide a maintenance message indicating that a specific memory board is to be replaced.

Abstract: An electronic assembly is made up of a number of electronic components. Each of the electronic components having a means for putting the component in a quiescent state while the remaining components are in a functional state, thereby enabling the testing of individual components without disassembly.

Abstract: A binary arithmetic unit performs arithmetic operations on binary coded decimal (BCD) operands by converting the BCD digits to hexadecimal excess 3 digits, generating hexadecimal excess 6 partial product digits and modifying selected excess 6 partial product digits to generate a BCD result.

Abstract: A computer system includes a first processor with main memory, an input/output processor with associated memory and an archival memory. Prior to reloading a new operating system from archival memory into the main memory, information such as timer information is stored in the input/output memory. The input/output memory continues to update the timer information until the second operating system is bootstrap loaded into the main memory. The timer and other information may then be returned to the first processor and main memory for use by the second operating system.

Abstract: A method for determining the maximum amount of physical memory present in a data processing system that can be configured to have one or more memory modules where the memory modules may be one of several types having different amounts of memory locations. By having signals indicating the presence of a memory module and the module type directly available with minimal intervening logic, a diagnostic process can accurately determine the amount of memory present in the system and reduce the possibility of a failed memory module going undetected. A method is also descibed using these memory module present and module type signals for detecting an attempt by either the central processor or an input/output controller to access a memory location that is not physically present within the data processing system.

Abstract: A method for performing margin justification in a word processing system by expanding the separation between words and between characters within words. Justifying lines of text by use of this method results in lines of text with an aesthetically pleasing uniform margin. The method uses the granular units of output devices so that one justification procedure can be used on all output devices.

Abstract: A method and apparatus for determining if matching units of an electronic system or a subsystem are assembled includes a single scratchpad memory which is addressed by the units on alternate cycles. A microprogram stored in one unit operates in synchronism with a microprogram in the other unit to write into and to test the contents of a location in scratchpad memory to determine if the two units would be operational with each other during normal operation.

Abstract: What is disclosed is a time partitioned bus arrangement for use in a computer system wherein different circuits therein are interconnected by a plurality of busses and operation is such that information to be processed can be read out of one circuit, processed in some manner in another circuit, and the processed information be stored in the same or another circuit all within one cycle of a system clock in the computer system, and without the need for bus control circuits and bus interfaces in the circuitry connected to the busses. Some of the circuits have their input/output connected to only a single one of the busses, while other circuits have their input connected to one bus and their output connected to a different bus, and yet other circuits have either their input or output connected to one of the busses and their other input/output connected to circuitry external to the bus arrangement.

Abstract: A split bus architecture which separates the processor/processors and the procedure memory coupled to a microprocessor (.mu.P) bus from all direct memory access (DMA) devices coupled to a DMA bus. A coupler mechanism provides bus isolation of the microprocessor bus from the DMA bus and permits the processor to access devices on the DMA side when addressed. This separation allows data transfers to proceed on one side of the bus without interfereing with software execution on the other side of the bus.

Abstract: In a Distributed Database System (DDS), database management and transaction management are extended to a distributed environment among a plurality of local sites which each have transaction server, file server, and data storage facilities. The Materialization and Access Planning (MAP) method of a distributed query, update, or transaction is an important part of the processing of the query, update, or transaction. Materialization and access planning results in a strategy for processing a query, update, or transaction in the distributed database management system (DSDBMS). Materialization consists of selecting data copies used to process the query, update, or transaction. This step is necessary since data may be stored at more than one site (i.e., computer) on the network. Access planing consists of choosing the execution order of operations and the actual execution site of each operation. Three access planning methods are used: General (Response), General (Total) and Initial Feasible Solution (IFS).

Abstract: An apparatus and a method for interfacing a commercially-available programmable communication interface (PIC) with a magnetic swipe reader or a wand type reader. The invention modifies the raw signals of the magnetic wand and magnetic swipe readers by removing noise and selecting the appropriate reader and track, stretching the clock pulses of the reader, and latching data into a flip-flop until the data is strobed into the PIC.

Abstract: A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an area of the display thereby clearly identifying adjacent areas of the display to the operator. The selected patterns are displayed in a REPLACE, an OR or an EXCLUSIVE OR mode of operation.

Abstract: An interactive terminal system transfers information at 750,000 bits per second between a central system and a number of work stations, all coupled in common to a single conductor coaxial bus. The central system prepolls an addressed work station before sending a block of information. The prepoll conditions the work station to prepare to receive a block of information.

Abstract: Local area network control block (LCB) hardware and a method is disclosed which forms a prime vehicle of intercommunication between controller coupled local area networks (LANs), comprising a plurality of computer systems. An LCB has a predetermined format and is assembled by the computer hardware to provide information to the controller regarding the routing and transfer of a variable quantity of data between LANs.

Abstract: A method for printing composite characters in a word processing system by multistriking two or more characters in the same character space. This method allows composite character graphics to be produced by using individual character graphics found within the character set of the output device. The method provides for the vertical and/or horizontal offsetting of the printhead between the striking of individual characters which form the composite character.

Abstract: A disk controller address register is used to address both a disk controller memory and a system memory between which data is transferred as it is stored on or retrieved from a disk storage device. A single address is provided to the address register which then develops other addresses needed in the data transfer between the two memories.

Abstract: A data entry terminal for use in a hostile environment is sealed from the outside environment. The terminal has a housing made up of a front panel, shroud and base plate that are fastened together in two different orientations to facilitate desk top and wall mounting, and electronic equipment is mounted inside the terminal enclosure. A fan circulates air around the inside of the terminal enclosure for cooling the electronic equipment inside. The enclosure base acts as a heat sink to transfer the heat to the outside environment in whatever position the terminal is mounted.

Abstract: A data processing system includes a central processor unit (CPU), a main memory and a memory management unit (MMU). Information is stored in main memory in segments, each segment being identified by a segment descriptor stored in a translation table in the MMU. Logical addresses from the CPU address segment descriptors in the MMU's translation table. These segment descriptors include the physical address of the location in main memory of the first word of the segment. If the segment descriptor is not in the translation table location, then the MMU operation is suspended while the segment descriptor is demand fetched from main memory.

Abstract: A method for achieving printed circuit (PC) board-level testability through electronic component-level design using available technological methods to effect a state of transparency during test, allowing precise verification and diagnosis on a component-by-component basis. Applicable to a greater variety of electronic products than other test methods, and not appreciably constraining functional design, this approach inherently avoids obstacles which prevent other techniques from fulfilling their objectives.

Abstract: A graphics display is cleared by apparatus forcing binary ZERO's into all locations of the bit map memories between successive vertical synchronization operations during a write refresh operation.